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datasheet single chip pc audio system codec+speaker amplifie r+capless hp+ldo+i2s 92HD92 idt confidential 1 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 description the 92HD92 single-chip audio system is a low power optimized, high fidelity, 4-channel audio codec with integrated speaker amplifier, capless headphone amplifier, and low drop out voltage regulator. dual high definition audio and i2s interfaces allow for docking and secondary audio support with a single codec. the integrated combo jack allows for dual-function headphone and headset detection. the integrated high-pass and band-pass filters allow for hardware eq and speaker protection. the high integration of the 92HD92 enables the smallest pcb footprint with the lowest system audio bom count and cost. the 92HD92 provides high qua lity hd audio capability to notebook and business de sktop pc applications. features ? 4 channels (2 stereo dacs and 2 stereo adcs) with 24-bit resolution ? supports full-duplex stereo audio and simultaneous voip ? provides a mono output ? 2.1 audio crossover support ? 2w/channel class-d stereo btl speaker amplifier @ 4 ohms and 5v ? 10 band hardware parametric equalizer ? hardware compressor limiter ? capless headphone amplifier with charge pump/ldo ? i2s support (2 input, 1 output) ? aux audio mode with i2c ? combo jack support allowing for dual-function headphone and headset detection ? speaker protection ? dedicated btl high pass filter ? mono bandpass filter ? full hda015-b low power support ? internal digital core ldo voltage regulator ? microsoft wlp desktop premium logo compliant ? dual spdif for wlp compliant support of simultaneous hdmi and spdif output ? support for 1.5v and 3.3v hda signaling ? two digital microphone inputs (mono, stereo, or quad microphones) ? high performance analog mixer ? 2 adjustable vref out pins for analog microphone bias ? 3 analog ports with port presence detect (2 single ended, 1 btl) ? digital pc beep support ? 48-pad qfn rohs package
idt confidential 2 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo full hda015-b low power support ? audio inactivity transitions codec from d0 to d3 low power mode ? resume from d3 to d0 with audio activity in < 10 msec ? d3 to d0 transition with < -65db pop/click ? port presence detect in d3 with or without bit clock ? pc beep wake up in d3 ? additional vendor specific modes for even lower power software support ? intuitive idt hd sound graphical user interfac e that allows configur ability and pr eference set- tings ? 12 band fully parametric equalizer ? constant, system-level effects tuned to optimize a particular platform can be combined with user-mode ?presets? tailored for specific acoustical environments and applications ? system-level effects automatically disabled when external audio connections made ? dynamics processing ? enables improved voice articulation ? compressor/limiter allows higher average volu me level without resonances or damage to speakers. ? idt vista apo wrapper ? enables multiple apos to be used with the idt driver ? microphone beam forming, acoustic ec ho cancellation, and noise suppression ? dynamic stream switching ? improved multi-streaming user experience with less support calls ? broad 3 rd party branded software includi ng creative, dolby, dts, and srs
idt confidential 3 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo table of contents 1. description ................................................................................................................ ........ 11 1.1. overview ................................................................................................................. .........................11 1.2. orderable part numbers ................................................................................................... ...............11 2. detailed description ..................................................................................................... 12 2.1. port functionality ............ .............. .............. .............. .............. .............. ............ ......... ......................12 2.1.1. port characteristics ............................. ...................................................................... .........12 2.1.2. vref_out ............................................................................................................... ..............14 2.1.3. jack detect ............................................................................................................ ............14 2.1.4. spdif output ........................................................................................................... ..........14 2.2. mono output .............................................................................................................. ......................16 2.3. mono output band-pass filter ............ .............. .............. .............. .............. .............. ........... ............17 2.3.1. filter description ................................. .................................................................... ...........17 2.4. mixer .................................................................................................................... ............................17 2.5. adc multiplexers ................................... ...................................................................... ....................17 2.6. power management ...... .............. .............. .............. .............. ........... ........... ........... .......... ................17 2.7. afg d0 ................................................................................................................... .........................18 2.8. afg d1 ................................................................................................................... .........................19 2.9. afg d2 ................................................................................................................... .........................19 2.10. afg d3 .................................................................................................................. ........................19 2.10.1. afg d3cold ............................................................................................................ .........19 2.11. vendor specific function group power states d4 /d5 ............ .............. .............. .............. ............19 2.12. low-voltage hda signaling ............................................................................................... ............20 2.13. multi-channel captur e ............... .............. .............. .............. .............. .............. .............. .................20 2.14. eapd .................................................................................................................... .........................22 2.15. digital microphone support .............................................................................................. .............25 2.16. analog pc-beep .......................................................................................................... ..................29 2.17. digital pc-beep ......................................................................................................... ....................31 2.18. headphone drivers ............. .............. .............. .............. .............. ........... ........... ............ .................32 2.19. btl amplifier ........................................................................................................... ......................32 2.20. btl amplifier high-pass filter .......................................................................................... .............32 2.20.1. filter description .................................................................................................... ..........33 2.21. eq ...................................................................................................................... ............................33 2.22. combo jack detection ................................. ................................................................... ...............33 2.23. gpio .................................................................................................................... ..........................34 2.23.1. gpio pin mapping and shared functions .........................................................................34 2.23.2. spdif/digital microphone/gpio selection ..... .............. .............. .............. .............. .........34 2.23.3. digital microphone/gpio selection .................................................................................34 2.24. hd audio hda015-b support ............................................................................................... .........34 2.25. digital core voltage regulator .......................................................................................... ............35 2.26. digital audio port (i2s) ................................................................................................ ..................36 2.26.1. characteristics ....................................................................................................... ..........36 2.26.2. left justified audio interface ........................................................................................ ....38 2.26.3. right justified audio inte rface (assuming n-bit word length ) ...........................................38 2.26.4. i2s format audio interface ............................................................................................ ..38 2.27. microphone mute input ................................................................................................... ...............38 2.28. aux audio support ....................................................................................................... ..................40 2.28.1. general conditions in aux audio mode: ...........................................................................40 2.28.2. entering aux audio mode ............................................................................................... .41 2.28.3. firmware/software requirements: ............... ....................................................................41 2.28.4. part options supporting i2s i/o ......................................................................................4 2 2.28.5. ?playback path? port behavior (digital i/o) ......................................................................42 2.28.6. when port e presence detect = 0 ....................................................................................42 2.28.7. when port e presence detect = 1 ....................................................................................42 2.28.8. ?record path? port behavior (digital i/o) .........................................................................43 2.28.9. eapd .................................................................................................................. .............44 2.28.10. class-d btl issues ................................................................................................... ....44 2.28.11. firmware/software requirements: .................................................................................44 2.28.12. system diagrams . .............. .............. .............. .............. ............ ........... ........... .........45
idt confidential 4 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 2.28.13. i2c control interface ................................................................................................ .......47 2.28.14. register write cycle ................................................................................................. .....47 2.28.15. multiple write cycle ........................... ...................................................................... ......47 2.29. register read cycle ............................... ...................................................................... .................48 2.29.1. multiple read cycle ................................................................................................... ......48 2.29.2. i2c registers ......................................................................................................... ..........49 3. characteristics ............................................................................................................ ... 72 3.1. electrical specifications ......................... ....................................................................... ...................72 3.1.1. absolute maximum ratings ............................................................................................... 72 3.1.2. recommended operating conditions ................................................................................72 3.2. 92HD92 analog performance characteristics (preliminary) ......................................................................73 3.3. class-d btl amplifier performance ................. ....................................................................... ........76 3.4. capless headphone supply characteristics ........ .............. .............. ........... ........... ........... ............ ...77 3.5. ac timing specs .......................................................................................................... ...................77 3.5.1. hd audio bus timing ............................. ....................................................................... .....77 3.5.2. spdif timing ........................................................................................................... ..........78 3.5.3. digital microphone timing ........................ ...................................................................... ...78 3.5.4. gpio characteristics ............................. ...................................................................... ......78 3.5.5. i2s interface timing ................................................................................................... ........79 4. functional block diagram .......................................................................................... 80 5. widget diagram ............................................................................................................. ... 81 6. port and pin configurations ..................................................................................... 82 6.1. port configurations ...................................................................................................... ....................82 6.2. pin configuration default register settings ... ........................................................................... .......83 7. widget information ........................................................................................................ 8 4 7.1. widget list .............................................................................................................. .........................85 7.2. reset key ................................................................................................................ ........................86 7.3. root (nid = 00h): vendorid ............................................................................................... .............86 7.3.1. root (nid = 00h): revid ................................................................................................ ....87 7.3.2. root (nid = 00h): nodeinfo ...................... ....................................................................... ..87 7.4. afg (nid = 01h): nodeinfo .. .............. .............. .............. .............. .............. .............. .......... .............88 7.4.1. afg (nid = 01h): fgtype ................................................................................................ .88 7.4.2. afg (nid = 01h): afgcap ................................................................................................ 89 7.4.3. afg (nid = 01h): pcmcap ...............................................................................................9 0 7.4.4. afg (nid = 01h): streamcap ............................................................................................9 1 7.4.5. afg (nid = 01h): inampcap .............................................................................................9 2 7.4.6. afg (nid = 01h): pwrstatecap .........................................................................................93 7.4.7. afg (nid = 01h): gpiocnt ............................................................................................... 94 7.4.8. afg (nid = 01h): outampcap ...................... ....................................................................94 7.4.9. afg (nid = 01h): pwrstate .............................................................................................. .95 7.4.10. afg (nid = 01h): unsolresp ...................... ....................................................................96 7.4.11. afg (nid = 01h): gpio ................................................................................................. ..96 7.4.12. afg (nid = 01h): gpioen ............................................................................................... 97 7.4.13. afg (nid = 01h): gpiodir .............................................................................................. 98 7.4.14. afg (nid = 01h): gpiowakeen .....................................................................................99 7.4.15. afg (nid = 01h): gpiounsol ........................................................................................100 7.4.16. afg (nid = 01h): gpiosti cky ............. .............. .............. .............. .............. ........... .......101 7.4.17. afg (nid = 01h): subid ................................................................................................ 101 7.4.18. afg (nid = 01h): gpioplrty ..........................................................................................10 2 7.4.19. afg (nid = 01h): gpiodrive .........................................................................................103 7.4.20. afg (nid = 01h): dmic ................................................................................................. .104 7.4.21. afg (nid = 01h): dacmode .........................................................................................105 7.4.22. afg (nid = 01h): adcmode .........................................................................................106 7.4.23. afg (nid = 01h): portuse .............................................................................................1 07 7.4.24. afg (nid = 01h): comjack ...........................................................................................108 7.4.25. afg (nid = 01h): vspwrstate ............. .............. .............. .............. .............. ........... .......109 7.4.26. afg (nid = 01h): anaport .............................................................................................1 10 7.4.27. afg (nid = 01h): anabtl .............................................................................................11 1 7.4.28. afg (nid = 01h): anabtlstatus ...................................................................................113
idt confidential 5 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.4.29. afg (nid = 01h): anacapless .......................................................................................113 7.4.30. afg (nid = 01h): reset ................................................................................................ .116 7.4.31. afg (nid = 01h): dac3outamp (mono out volume) ...................................................117 7.4.32. afg (nid = 01h): dac5outampleft (auxmode ) ...........................................................118 7.4.33. afg (nid = 01h): dac5outampright (auxm ode) ........................................................118 7.4.34. afg (nid = 01h): adc4outampleft (auxmode ) ...........................................................118 7.4.35. afg (nid = 01h): adc4outampright (auxm ode) ........................................................119 7.4.36. afg (nid = 01h): i2sctrl .............................................................................................. .120 7.4.37. afg (nid = 01h): eapd ..... .............. .............. .............. .............. .............. ........... ..........1 21 7.5. porta (nid = 0ah): wcap .................................................................................................. ............123 7.5.1. porta (nid = 0ah): pincap ....................... ....................................................................... 124 7.5.2. porta (nid = 0ah): conlst .............................................................................................. .125 7.5.3. porta (nid = 0ah): conlstentry0 ............... .....................................................................126 7.5.4. porta (nid = 0ah): inampleft ..........................................................................................1 26 7.5.5. porta (nid = 0ah): inampright .......................................................................................127 7.5.6. porta (nid = 0ah): conselectctrl ............... .....................................................................127 7.5.7. porta (nid = 0ah): pwrstate ...........................................................................................1 28 7.5.8. porta (nid = 0ah): pinwcntrl ..........................................................................................1 28 7.5.9. porta (nid = 0ah): unsolresp ................... .....................................................................129 7.5.10. porta (nid = 0ah): chsense .........................................................................................130 7.5.11. porta (nid = 0ah): eapdbtll r .............. .............. .............. ............ ........... ........... .......130 7.5.12. porta (nid = 0ah): configdefault ............. .....................................................................131 7.6. portb (nid = 0bh): wcap .................................................................................................. ............133 7.6.1. portb (nid = 0bh): pincap ....................... ....................................................................... 135 7.6.2. portb (nid = 0bh): conlst .............................................................................................. .136 7.6.3. portb (nid = 0bh): conlstentry0 ............... .....................................................................137 7.6.4. portb (nid = 0bh): conselectctrl ............... .....................................................................137 7.6.5. portb (nid = 0bh): pwrstate ...........................................................................................1 37 7.6.6. portb (nid = 0bh): pinwcntrl ..........................................................................................1 38 7.6.7. portb (nid = 0bh): unsolresp ................... .....................................................................139 7.6.8. portb (nid = 0bh): chsense ...........................................................................................13 9 7.6.9. portb (nid = 0bh): eapdbtll r .............. .............. .............. .............. ........... ........... .......140 7.6.10. portb (nid = 0bh): configdefault ............. .....................................................................140 7.7. (nid = 0ch): vendor reserved ...................... ....................................................................... .........143 7.8. portd (nid = 0dh): wcap .................................................................................................. ...........144 7.8.1. portd (nid = 0dh): pincap ......................... ..................................................................... 145 7.8.2. portd (nid = 0dh): conlst .............................................................................................. 146 7.8.3. portd (nid = 0dh): conlstentry0 ....................................................................................147 7.8.4. portd (nid = 0dh): conselectctrl .............. .....................................................................147 7.8.5. portd (nid = 0dh): pwrstate ...........................................................................................1 48 7.8.6. portd (nid = 0dh): pinwcntrl .........................................................................................14 9 7.8.7. portd (nid = 0dh): eapdbtllr .............. .............. .............. .............. ........... ........... .......149 7.8.8. portd (nid = 0dh): configdefault ............... .....................................................................149 7.9. porte (nid = 0eh): wcap (i2s output) ..................................................................................... ....153 7.9.1. porte (nid = 0eh): pincap ....................... ....................................................................... 154 7.9.2. porte (nid = 0eh): conlst .............................................................................................. .155 7.9.3. porte (nid = 0eh): conlstentry0 ............... .....................................................................156 7.9.4. porte (nid = 0eh): outampleft .......................................................................................156 7.9.5. porte (nid = 0eh): outampright ....................................................................................157 7.9.6. porte (nid = 0eh): conselectctrl ............... .....................................................................157 7.9.7. porte (nid = 0eh): pwrstate ...........................................................................................1 58 7.9.8. porte (nid = 0eh): pinwcntrl ..........................................................................................1 59 7.9.9. porte (nid = 0eh): unsolresp ................... .....................................................................159 7.9.10. porte (nid = 0eh): chsense .........................................................................................160 7.9.11. porte (nid = 0eh): eapdbtll r .............. .............. .............. ............ ........... ........... .......160 7.9.12. porte (nid = 0eh): configdefault ............. .....................................................................161 7.10. portf (nid = 0fh): wcap (i2s input) ..................................................................................... .....164 7.10.1. portf (nid = 0fh): pincap ............................................................................................. 165 7.10.2. portf (nid = 0fh): conlst ............................................................................................. 166
idt confidential 6 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.10.3. portf (nid = 0fh): conlstentry0 ...................................................................................167 7.10.4. portf (nid = 0fh): inampleft ........................................................................................16 7 7.10.5. portf (nid = 0fh): inampright ......................................................................................168 7.10.6. portf (nid = 0fh): conselectctrl ..................................................................................168 7.10.7. portf (nid = 0fh): pwrstate ................... .......................................................................1 69 7.10.8. portf (nid = 0fh): pinwcntrl ........................................................................................16 9 7.10.9. portf (nid = 0fh): unsolresp .......................................................................................170 7.10.10. portf (nid = 0fh): chsense ........................................................................................171 7.10.11. portf (nid = 0fh): eapdbtllr .................................................................................171 7.10.12. portf (nid = 0fh): involleft ........................................................................................1 72 7.10.13. portf (nid = 0fh): involright ................. .............. .............. ............ ........... ........... .......17 2 7.10.14. portf (nid = 0fh): configdefault ............ .....................................................................173 7.11. monoout (nid = 10h): wcap ............................................................................................... .......176 7.11.1. monoout (nid = 10h): pincap .......................................................................................177 7.11.2. monoout (nid = 10h): conlst .......................................................................................178 7.11.3. monoout (nid = 10h): conlstentry0 .............................................................................179 7.11.4. monoout (nid = 10h): pwrstate ....................................................................................179 7.11.5. monoout (nid = 10h): pinwcntrl ..................................................................................180 7.11.6. monoout (nid = 10h): conf igdefault .............................................................................181 7.12. dmic0 (nid = 11h): wcap ................................................................................................. ..........184 7.12.1. dmic0 (nid = 11h): pincap ...........................................................................................18 5 7.12.2. dmic0 (nid = 11h): inampleft .......................................................................................186 7.12.3. dmic0 (nid = 11h): inampright ....................................................................................187 7.12.4. dmic0 (nid = 11h): pwrstate .........................................................................................18 7 7.12.5. dmic0 (nid = 11h): pinwcntrl .......................................................................................188 7.12.6. dmic0 (nid = 11h): unsolresp ......................................................................................189 7.12.7. dmic0 (nid = 11h): chsense ........................................................................................189 7.12.8. dmic0 (nid = 11h): configdefault .................................................................................190 7.13. dmic1vol (nid = 12h): wcap ...................... ........................................................................ ........193 7.13.1. dmic1vol (nid = 12h): conlst ............. .............. .............. .............. .............. ........... .......194 7.13.2. dmic1vol (nid = 12h): conl stentry0 ..... .............. .............. .............. ........... ........... .......195 7.13.3. dmic1vol (nid = 12h): inam pleft ................ .............. .............. .............. .............. ..........195 7.13.4. dmic1vol (nid = 12h): inam pright ............. .............. .............. .............. .............. ..........195 7.13.5. dmic1vol (nid = 12h): pwrs tate ............ .............. .............. .............. ........... ........... .......196 7.14. dac0 (nid = 13h): wcap .................................................................................................. ..........197 7.14.1. dac0 (nid = 13h): cnvtr ............................................................................................... 198 7.14.2. dac0 (nid = 13h): outampleft ................... ..................................................................199 7.14.3. dac0 (nid = 13h): outampright ................ ..................................................................200 7.14.4. dac0 (nid = 13h): pwrstate .................... .....................................................................200 7.14.5. dac0 (nid = 13h): cnvtrid ............................................................................................2 01 7.14.6. dac0 (nid = 13h) : eapdbtllr ............ .............. .............. .............. ........... ........... .......202 7.15. dac1 (nid = 14h): wcap .................................................................................................. ..........202 7.15.1. dac1 (nid = 14h): cnvtr ............................................................................................... 204 7.15.2. dac1 (nid = 14h): outampleft ................... ..................................................................205 7.15.3. dac1 (nid = 14h): outampright ................ ..................................................................205 7.15.4. dac1 (nid = 14h): pwrstate .................... .....................................................................206 7.15.5. dac1 (nid = 14h): cnvtrid ............................................................................................2 07 7.15.6. dac1 (nid = 14h) : eapdbtllr ............ .............. .............. .............. ........... ........... .......207 7.16. adc0 (nid = 15h): wcap .................................................................................................. ..........208 7.16.1. adc0 (nid = 15h): conlst ............................................................................................20 9 7.16.2. adc0 (nid = 15h): conlstentry0 ..................................................................................210 7.16.3. adc0 (nid = 15h): cnvtr ............................................................................................... 210 7.16.4. adc0 (nid = 15h): procstate ........................................................................................211 7.16.5. adc0 (nid = 15h): pwrstate .................... .....................................................................212 7.16.6. adc0 (nid = 15h): cnvtrid ............................................................................................2 13 7.17. adc1 (nid = 1bh): wcap .................................................................................................. .........213 7.17.1. adc1 (nid = 1bh): conlst ....................... .....................................................................21 5 7.17.2. adc1 (nid = 1bh): conlstentry0 ............. .....................................................................215 7.17.3. adc1 (nid = 1bh): cnvtr ............................................................................................... 216
idt confidential 7 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.17.4. adc1 (nid = 1bh): procstate ........................................................................................217 7.17.5. adc1 (nid = 1bh): pwrstate .........................................................................................218 7.17.6. adc1 (nid = 1bh): cnvtrid ...........................................................................................21 9 7.18. adc0mux (nid = 17h): wcap ............................................................................................... ......220 7.18.1. adc0mux (nid = 17h): conlst ......................................................................................221 7.18.2. adc0mux (nid = 17h): conlstentry4 ...........................................................................222 7.18.3. adc0mux (nid = 17h): conlstentry0 ...........................................................................222 7.18.4. adc0mux (nid = 17h): outampcap .............. ...............................................................223 7.18.5. adc0mux (nid = 17h): outampleft ............ ..................................................................223 7.18.6. adc0mux (nid = 17h): outampright ......... ..................................................................224 7.18.7. adc0mux (nid = 17h): conselectctrl ......... ..................................................................224 7.18.8. adc0mux (nid = 17h): pwrs tate ..................................................................................225 7.18.9. adc0mux (nid = 17h): eapd btllr ............. .............. .............. .............. .............. .......226 7.19. adc1mux (nid = 18h): wcap ............................................................................................... ......226 7.19.1. adc1mux (nid = 18h): conlst ......................................................................................228 7.19.2. adc1mux (nid = 18h): conlstentry4 ...........................................................................228 7.19.3. adc1mux (nid = 18h): conlstentry0 ...........................................................................229 7.19.4. adc1mux (nid = 18h): outampcap .............. ...............................................................229 7.19.5. adc1mux (nid = 18h): outampleft ............ ..................................................................230 7.19.6. adc1mux (nid = 18h): outampright ......... ..................................................................230 7.19.7. adc1mux (nid = 18h): conselectctrl ......... ..................................................................231 7.19.8. adc1mux (nid = 18h): pwrs tate ..................................................................................231 7.19.9. adc1mux (nid = 18h): eapd btllr ............. .............. .............. .............. .............. .......232 7.20. monomux (nid = 19h): wcap ............................................................................................... ......233 7.20.1. monomux (nid = 19h): conls t ............... .............. .............. .............. ........... ........... .......234 7.20.2. monomux (nid = 19h): conlstentry0 .......... .............. .............. .............. .............. ..........235 7.20.3. monomux (nid = 19h): conselectctrl ...........................................................................235 7.20.4. monomux (nid = 19h): pwrstate ................. ..................................................................235 7.21. monomix (nid = 1ah): wcap ............................................................................................... .......236 7.21.1. monomix (nid = 1ah): conlst .......................................................................................238 7.21.2. monomix (nid = 1ah): conlstentry0 ........... ..................................................................238 7.21.3. monomix (nid = 1ah): pwrstate ....................................................................................239 7.22. mixer (nid = 1bh): wcap ................................................................................................. ...........241 7.22.1. mixer (nid = 1bh): inampcap .......................................................................................242 7.22.2. mixer (nid = 1bh): conlst ............................................................................................. 243 7.22.3. mixer (nid = 1bh): conlstentry4 ............. .....................................................................243 7.22.4. mixer (nid = 1bh): conlstentry0 ............. .....................................................................244 7.22.5. mixer (nid = 1bh): inampleft0 ......................................................................................244 7.22.6. mixer (nid = 1bh): inampright0 ...................................................................................245 7.22.7. mixer (nid = 1bh): inampleft1 ......................................................................................245 7.22.8. mixer (nid = 1bh): inampright1 ...................................................................................246 7.22.9. mixer (nid = 1bh): inampleft2 ......................................................................................246 7.22.10. mixer (nid = 1bh): inampright2 .................................................................................247 7.22.11. mixer (nid = 1bh): inampleft3 ............... .....................................................................247 7.22.12. mixer (nid = 1bh): inampright3 .................................................................................248 7.22.13. mixer (nid = 1bh): inampleft4 ............... .....................................................................248 7.22.14. mixer (nid = 1bh): inampright4 .................................................................................249 7.22.15. mixer (nid = 1bh): inampleft5 ............... .....................................................................249 7.22.16. mixer (nid = 1bh): inampright5 .................................................................................250 7.22.17. mixer (nid = 1bh): pwrstate ........................................................................................25 0 7.23. mixeroutvol (nid = 1ch): wcap ........................................................................................... ......251 7.23.1. mixeroutvol (nid = 1ch): conlst ..................................................................................253 7.23.2. mixeroutvol (nid = 1ch): conlstentry0 ..... ..................................................................253 7.23.3. mixeroutvol (nid = 1ch): outampcap .........................................................................254 7.23.4. mixeroutvol (nid = 1ch): outampleft ..........................................................................255 7.23.5. mixeroutvol (nid = 1ch): outampright .......................................................................255 7.23.6. mixeroutvol (nid = 1ch): pwrstate ......... .....................................................................256 7.24. spdifout0 (nid = 1dh): wcap ............................................................................................. .....257 7.24.1. spdifout0 (nid = 1dh): pcmcap ................................................................................258
idt confidential 8 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.24.2. spdifout0 (nid = 1dh): streamcap ............................................................................260 7.24.3. spdifout0 (nid = 1dh): outampcap ......... ..................................................................260 7.24.4. spdifout0 (nid = 1dh): cnvtr ......................................................................................261 7.24.5. spdifout0 (nid = 1dh): outampleft ...........................................................................262 7.24.6. spdifout0 (nid = 1dh): outampright .........................................................................263 7.24.7. spdifout0 (nid = 1dh): pwrstate .............. ..................................................................263 7.24.8. spdifout0 (nid = 1dh): cnvtrid ..................................................................................264 7.24.9. spdifout0 (nid = 1dh): digcnvtr ................................................................................265 7.25. spdifout1 (nid = 1eh): wcap ............................................................................................. .....266 7.25.1. spdifout1 (nid = 1eh): pcmcap .............. ..................................................................267 7.25.2. spdifout1 (nid = 1eh): streamcap ............................................................................269 7.25.3. spdifout1 (nid = 1eh): outampcap ......... ..................................................................269 7.25.4. spdifout1 (nid = 1eh): cnvtr ......................................................................................270 7.25.5. spdifout1 (nid = 1eh): outampleft ......... ..................................................................271 7.25.6. spdifout1 (nid = 1eh): outampright ....... ..................................................................272 7.25.7. spdifout1 (nid = 1eh): pwrstate .............. ..................................................................272 7.25.8. spdifout1 (nid = 1eh): cnvtrid ..................................................................................273 7.25.9. spdifout1 (nid = 1eh): digcnvtr ............ .....................................................................274 7.26. dig0pin (nid = 1fh): wcap ............................................................................................... .........275 7.26.1. dig0pin (nid = 1fh): pincap .........................................................................................27 6 7.26.2. dig0pin (nid = 1fh): conlst .........................................................................................27 7 7.26.3. dig0pin (nid = 1fh): conlst entry0 ...............................................................................278 7.26.4. dig0pin (nid = 1fh): pwrstate ................. .....................................................................278 7.26.5. dig0pin (nid = 1fh): pinwcntrl ....................................................................................279 7.26.6. dig0pin (nid = 1fh): unsolresp ..................................................................................280 7.26.7. dig0pin (nid = 1fh): chsense ................. .....................................................................280 7.26.8. dig0pin (nid = 1fh): config default ...............................................................................281 7.27. dig1pin (nid = 20h): wcap ............................................................................................... ..........283 7.27.1. dig1pin (nid = 20h): pincap .................... .....................................................................28 5 7.27.2. dig1pin (nid = 20h): conlst .........................................................................................28 6 7.27.3. dig1pin (nid = 20h): conlstentry0 ...............................................................................287 7.27.4. dig1pin (nid = 20h): pwrsta te ......................................................................................287 7.27.5. dig1pin (nid = 20h): pinwcntrl .....................................................................................288 7.27.6. dig1pin (nid = 20h): configdefault .......... .....................................................................289 7.28. digbeep (nid = 21h): wcap .......................... ..................................................................... ........292 7.28.1. digbeep (nid = 21h): outampcap .............. ..................................................................293 7.28.2. digbeep (nid = 21h): outa mpleft ................................................................................293 7.28.3. digbeep (nid = 21h): pwrsta te .....................................................................................294 7.28.4. digbeep (nid = 21h): gen .............................................................................................2 95 7.28.5. digbeep (nid = 21h): gain ..................... .......................................................................2 95 7.29. i2c (nid = 22h): wcap ................................................................................................... .............296 7.29.1. i2c (nid = 22h): cntrl0 ............................................................................................... ...297 8. pinout and packaging .................................................................................................. 299 8.0.1. 48qfn pin table ........................................................................................................ .....300 8.0.2. 48qfn package outline and package dimensions ........................................................302 8.1. standard reflow profile data ............................................................................................. ...........303 9. disclaimer ................................................................................................................. ........ 304 10. document revision history ..................................................................................... 305
idt confidential 9 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo list of tables table 1. port functionality ................................................................................................... ..........................12 table 2. analog output port behavior ................. ......................................................................... .................13 table 3. 48pin jack detect .................................................................................................... ........................14 table 4. spdif out 0 behavior .......................... ....................................................................... ...................15 table 5. spdif out 1 behavior .......................... ....................................................................... ...................15 table 6. power management ........... .............. .............. .............. .............. ........... ............ ........... ....................18 table 7. example channel mapping ........................ ...................................................................... .................20 table 9. eapd pin mode select .......................... ....................................................................... ...................23 table 10. control bit descriptions for btl amplifier a nd headphone amplifier enable configurations ...........23 table 11. btl amp enable configurat ion ........................................................................................ ..............23 table 12. headphone amp enable configuration .............. .............. .............. .............. .............. ............ ........23 table 14. eapd analog pc_beep behav ior ............. .............. .............. .............. ............ ........... .......... ..........24 table 15. eapd behavior ............. .............. .............. .............. .............. ............ ........... ........... .......................24 table 13. port e headphone amp enable configuration sup port by part and mode ... .............. ........... .........24 table 16. valid digital mic configurations ........... ......................................................................... .................26 table 17. dmic_clk and dmic_0,1 operation during powe r states ..........................................................26 table 18. sclk frequency selection ............ .............. .............. .............. .............. .............. .......... ................36 table 19. mclk frequency selection ............................................................................................ ...............37 table 20. i2c registers ....................................................................................................... ..........................49 table 21. electrical specification: maximum ratings .......................................................................... .........72 table 22. recommended operating conditions .................................................................................... ........72 table 23. 92HD92 analog performance characteristics ... ........................................................................ ....73 table 24. class-d btl amplifier performance ................................................................................... ...........76 table 25. capless headphone supply ........................ .................................................................... ..............77 table 26. hd audio bus timing ................................................................................................. ....................77 table 27. spdif timing ........................................................................................................ .........................78 table 28. digital mic timing ............................ ...................................................................... ..........................78 table 29. gpio characteristics ................................................................................................ .....................78 table 30. i2s interface timing ................................................................................................ .......................79 table 31. pin configuration default settings .......... ........................................................................ ...............83 table 32. command format for verb with 4-bit identifier ............. .............. ........... ........... ............ .......... .......84 table 33. command format for verb with 12-bit identifi er ...................................................................... ......84 table 34. solicited response format ........................................................................................... .................84 table 35. unsolicited response format ......................................................................................... ...............84 table 36. widget list ............... .............. .............. .............. .............. .............. ........... ......... ............................85 table 37. pin table ........................................................................................................... ...........................300 table 38. standard reflow profile .............. .............. .............. .............. .............. ............ ........... ..................303
idt confidential 10 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo list of figures figure 1. multi-channel capture ... .............. .............. .............. .............. .............. ........... ........... .......................21 figure 2. multi-channel timing diagr am ............. .............. .............. .............. ........... ........... ........... ..................21 figure 3. hp eapd example to be replaced by single pin for internal amp ............. .............. .............. .........25 figure 4. eapd implementation ................................................................................................. ....................25 figure 5. single digital microphone (data is ported to both left and right channels .. .............. .............. .........27 figure 6. stereo digital microphone configuration ............................................................................. ...........28 figure 7. quad digital microphone configuration ........ ....................................................................... ...........29 figure 8. analog pc beep active ........................ ....................................................................... ...................30 figure 9. analog pc beep flow chart .................. ......................................................................... .................31 figure 10. combo jack ......................................................................................................... .........................33 figure 11. left justified audio interface (assuming 24-bit word length) ....................................................... .38 figure 12. right justified audio interface (assuming 24-bi t word length) ...................................................... 38 figure 13. i2s justified audio interface (assuming 24-bit word length) ........................................................ .38 figure 14. switching between normal and aux audio modes .............. .............. .............. .............. ............... 41 figure 15. playback path on parts supporting digital i/o ...................................................................... .......45 figure 16. record path on parts supporting digital i/o ........................................................................ ........46 figure 17. 2-wire serial control interface ............ ........................................................................ ..................47 figure 18. multiple write cycle ......................... ...................................................................... .......................48 figure 19. read cycle ......................................................................................................... ..........................48 figure 20. multiple read cycle ... ............................................................................................. ......................49 figure 21. hd audio bus timing ................................................................................................ ....................77 figure 22. functional block diagram ........................................................................................... ..................80 figure 23. widget diagram ..................................................................................................... .......................81 figure 24. port configurations ................................................................................................ .......................82 figure 25. ................................................................................................................... ...................................83 figure 26. 48qfn pin assignment ............................................................................................... ...............299 figure 27. 48qfn package diagram .............................................................................................. .............302
idt confidential 11 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 1. description 1.1. overview the 92HD92 audio codec provides stereo 24- bit, fu ll duplex resolution supporting sample rates up to 192khz by the dac and adc. spdif outputs su pport sample rates of 192khz, 96khz, 88.2khz, 48khz, and 44.1khz. additional sample ra tes are supported by the driver software. an integrated btl stereo amplifie r is ideal for driving 4ohm or 8ohm integrated speakers in mobile and ultra-mobile computers. for desktop computer s or mobile computers using only one speaker, the btl output stage may be configured to support a single mono speaker. the 92HD92 audio codec supports a wide range of desktop and laptop configurations. the 2 inde- pendent spdif output interfaces provide connectiv ity to consumer electronic equipment or to a home entertainment system. simultaneous hdmi and spdif output is possible. all inputs can be programmed with 0-30 db gain in 10 db steps allowing for line or microphone use of any input. port presence detect capabilitie s allow the codec to detect when audio devices are connected to the codec. the fully parametric internal eq can be initiated upon headphone jack insertion and removal for protection of notebook speakers. the 92HD92 audio codec operates with a 3.3v digi tal supply and a 5v (4.7 5v allowed when using external voltage regulator) analog supply. it allows for 1.5v and 3.3v hda signaling; the correct sig- nalling level is selected dynamically based on the power supply voltage on the dvdd-io pin. the 92HD92 audio codec is offered in a 48-pin qfn environmental (rohs) package. 1.2. orderable part numbers yy = silicon stepping/revision, contact sales for current data. add an ?8? to the end for tape and reel delivery. 92HD92b1x5nlgxyyx aux mode 92HD92b2x5nlgxyyx no aux mode
idt confidential 12 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 2. detailed description 2.1. port functionality multi-function (input/outpu t) ports allow for the highest possible flexibility and supporting a wide vari- ety of consumer desktop and mobile system use models. ? port a supports ? headphone out ? line out ? line input ? mic with 0/10/20/30 db boost ? port b supports ? capless headphone out ? capless line out ? port d supports ? btl stereo output ? btl (l+/l-) mono out ? port e supports ? headpone out ? line out (i2s) ? port f supports ? line in (i2s) ? mic with 0/10/20/30 db boost and vref_out ? mono out supports ? line out note: pins 15/16/18 are shared for i2s clocking. port c is vendor re served for this device 2.1.1. port characteristics universal (bi-directional) jacks are supported on ports a, e, and f for all family members. ports a and b are designed to drive 32 ohm (nominal) headphones or a 10k (nominal) load. line level out- puts are intended to drive an external 10k load (nominal) and an on board shunt resistor of 20-47k (nominal). however, applications may support load impedances of 5k ohms and above. input ports are 50k (nominal) at the pin. pins 48-qfn port input output headphone btl mic bias (vref pin) input boost amp 28/29 a yes yes yes yes yes 31/32 b yes yes 40/41/43/44 d yes yes 17 e yes i2s yes yes 24 f yes i2s yes 25 mono out yes 48 spdif_out0 yes 46 dmic1/spdifout1/ aux_in yes yes yes 4 (clk=2) dmic0 yes yes table 1. port functionality
idt confidential 13 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo dac full scale outputs and intended full scale input levels are 1v rms at 5v. line output ports and headphone output ports on the 92HD92 codec may be configured for +3dbv full scale output levels by using a vendor specific verb. output ports are always on to prevent pops/clicks associated with charging and discharging output coupling capacitors. this maintains proper bias on output coupling caps even in power state d3 as long as avdd is available. unused ports shou ld be left unconnected. when updating existing designs to use the codec, ensure that there are no conflicts between the output ports on the codec and existing circuitry . afg power state input enable output enable used as output for dac/mixer used as output for analog pc_beep used as input for adc, mixer port behavior d0-d2 1 1 don't care don't care yes not allowed. port is active as input. no not allowed. inactive (power down) - port keeps output coupling caps charged if port uses caps. 1 0 na na yes active - port enabled as input 1 0 na na no inactive (power down) - port keeps output coupling caps charged if port uses caps. 01 currently used by dac, mixer, beep, or is traditional line or headphone output na active - port enabled as output 01 not currently used by dac, mixer, beep and is capless hp/btl port inactive (power down) 0 0 na na na inactive (power down) - port keeps output coupling caps charged if port uses caps. d3 1 1 na na don't care not allowed. inactive (power down) - port keeps output coupling caps charged if port uses caps. 1 0 na na don't care inactive (power down) - port keeps output coupling caps charged if port uses caps. 01 currently used by dac, mixer, beep, or is traditional line or headphone output don't care low power state. if enabled, beep will output from the port 01 not currently used by dac, mixer, beep and is capless hp/btl port don't care inactive (power down) 0 0 na na don't care inactive (power down) - port keeps output coupling caps charged if port uses caps. d3cold - - inactive (lower power) - port keeps output coupling caps charged if port uses caps. d4 - - inactive (lower power) - port keeps output coupling caps charged if port uses caps. d5 - - off - charge on coupling caps (if used) will not be maintained. table 2. analog output port behavior
idt confidential 14 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 2.1.2. vref_out port a supports vref_out pins for biasing electr et cartridge microphones. settings of 80% avdd, 50% avdd, gnd, and hi-z are supported. attempting to program a pin widget control with a reserved or unsupported value will cause the asso ciated vref_out pin to assume a hi-z state and the pin widget control vref_en field will retu rn a value of ?000 ? (hi-z) when read. 2.1.3. jack detect plugs inserted to a jack on ports a, b & spdifou t0 are detected using sense_a. plugs inserted to a jack on ports e, f, dmic 0, & spdifout1 are detected us ing sense_b. per hda015-b, the detection circuit operates when the codec is in d0 - d3 and can also operate if both the codec and controller are in d3 (no bus clock.) jack detecti on requires that all supplies (analog and digital) are active and stable. when avdd is not present, the value reported in the pin widget is invalid. when the hd audio bus is in a low power state (r eset asserted and cloc k stopped) the codec will generate a power state change request when a change in port connectivity is sensed and then generate an unsolicited response after the hd audio link has been brought out of a low power state and the device has been enum erated. per hda015-b, this will take less than 10ms. the following table summarizes the proper resistor tolerances for different analog supply voltages.. see reference design for more information on jack detect implementation. 2.1.4. spdif output both spdif outputs can operate at 44.1khz, 48khz, 88.2 khz, 96khz and 192khz as defined in the intel high definition audio specific ation with resolutions up to 24 bi ts. this insures compatibility with all consumer audio gear and allows for convenient integration into home theater systems and media center pcs. the two spdif output converters can not be alig ned in phase with the dacs. even when attached to the same stream, the two spdif output converte rs may be misaligned with respect to their frame boundaries. per the hda015-b, the spdif output s support the ability to provide clocking information even when no stream is selected for the converter, or when in a low power state. also, the spdif output ports support port presence detect. avdd nominal voltage (+/- 5%) resistor tolerance pull-up resistor tolerance sense_a/b 4.75v 1% 1% resistor sense_a sense_b 39.2k port a (hp0) port e 20.0k port b (hp1) port f 10.0k na dmic0 5.11k spdifout0 spdifout1 (dmic1) 2.49k pull-up to avdd pull-up to avdd table 3. 48pin jack detect
idt confidential 15 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo spdif outputs are outlined in tables below. afg power state reset# output enable converter dig enable stream id keep alive enable pin behavior d0-d3 asserted (low) - - - - hi-z (internal pull-down enabled) immediately after power on, otherwise the prev ious state is retained. d0 de-asserted (high) disabled - - - hi-z (internal pull-down enabled) de-asserted (high) enabled disabled - - active - pin drives 0 (internal pull-down na) de-asserted (high) enabled enabled 0 - active - pin drives spdif-format, but data is zeroes (internal pull-down na) de-asserted (high) enabled enabled 1-15 - active - pin drives spdifout0 data (internal pull-down na) d1-d2 de-asserted (high) disabled - - - hi-z (internal pull-down enabled) de-asserted (high) enabled - - 0 active - pin drives 0 (internal pull-down na) enabled - 1 active - pin drives spdif-format, but data is zeroes (internal pull-down na) d3 de-asserted (high) - - - 0 hi-z (internal pull-down enabled) disabled - - 1 hi-z (internal pull-down enabled) enabled enabled - 1 active - pin drives spdif-format, but data is zeroes (internal pull-down na) d3cold - - - - - hi-z (internal pull-down enabled) d4 - - - - - hi-z (port off) d5 - - - - - hi-z (port off) table 4. spdif out 0 behavior afg power state reset# gpio0 enable input enable output enable converter dig en stream id keep alive en pin behavior d0-d3asserted (low)---- -- hi-z (internal pull-down enabled) immediately after power on, otherwise the previous state is retained. d0-d3 de-asserted (high) enabled - - - - - active - pin reflects gpio0 configuration (internal pull-down enabled) d0-d3 de-asserted (high) disabled enabled disabled - - - pin functions as digital mic input (internal pull-down enabled) table 5. spdif out 1 behavior
idt confidential 16 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 2.2. mono output the mono out port source selection, power state, and mute characteristics are all independently controlled by the mono output port controls. eq d oes not apply to this path. an internal 2nd order band-pass filter is provided to restrict the output frequencies when using mono out to drive an exter- nal amplified sub-woofer. the following sources are available for the mono out pin: ? dac0 output: when selected (by using the port connection list), the dac0 left and right outputs are summed together. ? dac1 output: when selected (by using the port connection list), the dac1 left and right outputs are summed together. ? mixer output: when selected (by using the port connection list), the mixer left and right outputs are summed together. the stereo inputs are scaled by -6db and then summ ed to provide an output that is the average of the two inputs. the full scale output at mono out is designed to be about 0dbv. it is not possible to adjust to a +3dbv output level. d0 de-asserted (high) disabled disabled disabled - - - hi-z (internal pull-down enabled) - enabled disabled - - active - pin drives 0 (internal pull-down na) enabled 0- active - pin drives spdif-format, but data is zeroes (internal pull-down na) 1-15 - active - pin drives spdifout1 data (internal pull-down na) d1-d2 de-asserted (high) disabled disabled disabled - - - hi-z (internal pull-down enabled) enabled disabled - - active - pin drives 0 (internal pull-down na) enabled -0 active - pin drives 0 (internal pull-down na) -1 active - pin drives spdif-format, but data is zeroes (internal pull-down na) d3 de-asserted (high) disabled disabled disabled - - - hi-z (internal pull-down enabled) enabled disabled - - hi-z (internal pull-down enabled) enabled - 0 hi-z (internal pull-down enabled) -1 active - pin drives spdif-format, but data is zeroes (internal pull-down na) d3cold - disabled disabled - - - - hi-z (internal pull-down enabled) d4- ---- --hi-z (port off) d5- ---- --hi-z (port off) afg power state reset# gpio0 enable input enable output enable converter dig en stream id keep alive en pin behavior table 5. spdif out 1 behavior
idt confidential 17 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 2.3. mono output band-pass filter for many applications, the primary speakers are incapable of reproducing low frequency audio. therefore it is desirable to implem ent a woofer or sub-woofer speake r. the mono output is ideal for this task. however, the frequency response should be restricted to prevent interference with the primary speakers. typically an external filter, known as a cross-over filter, is used. the mono processing path includes a band-pass filter with programmable high and low cut-off frequencies to eliminate the need for an external filter. 2.3.1. filter description the band-pass filter is derived from the common biquadratic filter and provides a 12db/octave roll-off. the filter may be programmed for a -3db lower band edge of: 63hz, 80hz, 100hz, 120hz, 150hz, 200hz, 315hz, or 400hz. the filter ma y be programmed for a -3db upper band edge of: 150hz, 200hz, 250hz, 315hz, 400hz, 500hz, 630hz, or 800hz. the band-pass filter is enabled by default with a cut-off frequencies at 120hz and 250hz. the filter may be bypassed using the associat ed verb (processi ng state verb). the analog pc_beep input is not affected by the band-pass filter. 2.4. mixer the mixer supports independent gain (-34.5 to +12db in 1.5db steps) on each input as well as inde- pendent mutes on each input. the following inputs are available: ?port a ?port f ?dac 0 ?dac 1 2.5. adc multiplexers the codec implements 2 adc input multiplexers. these multiplexers incor porate the adc record gain function :(-16 to +30db gain in 1db steps) as an output amp and allow a preselection of one of below possible inputs: ?port a ?port f ? mixer output ?dmic 0 ?dmic 1 2.6. power management the hd audio specification defines power states, power state widgets, and power state verbs. power management is implemented at several leve ls. the audio function group (afg) , all con- verter widgets, and all pin complexes support the power state verb f05/705. converter widgets are active in d0 and inactive in d1-d3.
idt confidential 18 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo the following table describes what function ality is active in each power state. the d3-default state is available for hd audio compliance. the programmable values, exposed via vendor-specific settings, are under idt device driver control for further power reduction. the analog mixer, line and headphone amps, port presence detect, and internal references may be disabled using vendor specific verbs. use of t hese vendor specific verbs will cause pops. the default power state for the audio function group after reset is d3. 2.7. afg d0 the afg d0 state is the active state for the device. all functions are active if their power state (if they support power management at their node level) has been set to d0. function d0 d1 1 1. no dac or adc streams are active. analog mixing and loop thru are supported . d2 d3 d3cold vendor specific d4 vendor specificd5 spdif outputs on on on (idle) on (idle) 5 off off off digital microphone inputs on off off off off off off dac on off off off off off off d2s on off off off off off off adc on off off off off off off adc volume control on off off off off off off ref adc on off off off off off off analog clocks on off off off off off off gpio pins on on on on 5 on on off vrefout pins on on off off off off off input boost on on off off off off off analog mixer on on off off off off off mixer volumes on on off off off off off digital pc_beep on on on on 5 off off off lo/hp amps on on on low drive 2 2. vag is kept active when ports are disabled or in d3/d3c old/d4. pc_beep is supported in d3 but may be attenuated and distorted depending on load impedance. t he codec will shut down the capless headphone amplifiers and btl amplifier in d3 and below. in d3, t he codec will turn on the btl and capless amplifiers if activity is detected on the pc_beep input and analog pc_beep is enabled. low drive 2 low drive 2 off capless hp amps on on on low drive 2 low drive 2 low drive 2 off btl amp on on on low drive 2 off off off vag amp on on on low drive 3 3. vag is always ramped up and down gradually, except in the case of a sudden power removal. vag is active in d2/d3 but in a low power state. low drive low drive off port sense ononon on 4 4. both avdd and dvdd must be avai lable for port sense to operate. off off off reference bias generator on on on on on on off reference bandgap core on on on on on on off hd audio-link on on on on 5 5. not active if bitclk is not running (controller in d3), but can signal power state change request (pme) limited off off table 6. power management
idt confidential 19 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 2.8. afg d1 d1 is a lower power mode where all converter wid gets are disabled. analog mixer and port functions are active. the part will resume from thed1 to thed0 state within 1 ms. 2.9. afg d2 the d2 state further reduces power by disabling t he mixer and port function s. the port amplifiers and internal references remain ac tive to keep port coupling caps charged and the system ready for a quick resume to either th e d1 or d0 state. the part will resume from the d2 stat e to the d0 state within 2ms. 2.10. afg d3 the d3-default state is available for hd audio compliance. all conver ters are shut down. port ampli- fiers and references are active but in a low power state to prevent pops. resume times may be lon- ger than those from d2, but still less than 10ms to meet intel low power goals. the default power state for the audio function group after power is applied is d3. while in afg d3, the hd audio controller may be in a d0 state (hd audio bus active) or in a d3 state (hd audio bus held in reset with no bit_clk, sdata_out, or sync activity.) the expected behav- ior is as follows (see the hda015- b section for more information): 2.10.1. afg d3cold the d3cold power state is the lowe st power state available that does not use vendor specific verbs. while in d3cold, the codec will still respond to bus requests to reve rt to a higher power state (dou- ble afg reset, link reset). however, audio processi ng, port presence detect, and other functions are disabled. per the hd audio bus hda015-b, the d3cold state is intended to be used just prior to removing power to the codec. ty pically, power will be removed wi thin 200ms. however, the codec may exit from the d3cold state by generating 2, back-to-back, afg reset events. resume time from d3cold is less than 200ms. 2.11. vendor specific function group power states d4/d5 the codec introduces vendor specific power states. a vendor defined verb is added to the audio function group that combines multiple vendor spec ific power control bits into logical power states for use by the audio driver. the 2 states defined of fer lower power than the 5 existing states defined in the hd audio specification and hda015-b. the vendor specific d4 state provides lower digital power consumption relative to d3co ld by disabling hd audio link responses. vendor specific d5 fur- ther reduces power consumption on the digital supply by turning off gpio drivers, and reduces ana- log power consumption by turning off all an alog circuitry except for reset circuits. states d4/d5 are not entered until d3cold has been requested so are actually d3cold options rather than true, independent, power states. software can pr e-program the d4 or d5 state as a re-definition of how the part will behav e when the d3cold power state is req uested or software may enter d3cold, then set the d4 or d5 before performing the po wer state get command. the preferred method is to request d3cold, then select d4 or d5 as desired.this will reduce th e severity of pops encountered when entering d4 or d5. function hda bus active hda bus stopped port presence detect state change unsolicited re sponse wake event followed by an unsolicited response gpio state change unsolicited response wake event followed by an unsolicited response
idt confidential 20 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo both power states require a link re set or removal of dvdd to exit. the codec may pop when using these verbs and transi tion times to an active state (d1 or d0 for example) may take several seconds. 2.12. low-voltage hda signaling the codec is compatible with eit her 1.5v or 3.3v hda bus signaling; in the 48-qfn package the voltage selection is done dynamically based on the input voltage of dvdd_io. dvdd_io is currently not a logic configuration pin, but rather provides the digital power supply to be used for the hda bus signals. when in 1.5v mode, the codec can correctly decode bitclk, sync, reset# and sdo as they operate at 1.5v; addition ally it will drive sdi and sdo at 1.5v . none of the gpios are affected, as they always function at their nominal voltage (dvdd or avdd). 2.13. multi-channel capture the capability to assign multiple adc converters to the same str eam is supported to meet the microphone array requirements of vista and future operating systems. single converter streams are still supported this is done by assi gning unique non zero stream ids to each converter. all capture devices (adcs 0 and 1) may be used to create a multi-channel input stream. there are no restric- tions regarding digital microphones. the adc converters can be associated with a single stream as long the sample rate and the bits per sample are the same. the assignment of converter to channel is done using the ?cnvtrid? widget and is restricted to even values. the adc conver ters will always put out a stereo sample and there- fore require 2 channels per converter. the stream will not be generated unle ss all entries for the targeted converters are set identically, and the total number of assigned converter channels ma tches the value in the nmbrchan field. these are listed the ?multi-converter stream critical entries.? table. an example of a 4 channel steam with adc0 supplying channels 0&1 and adc1 supplying chan- nels 2 & 3 is shown below. a 4 channel stream can be created by assigning the same non-zero stream id ?strm= n? to both adc0 and adc1. the sample rates must be se t the same and the num- ber of channels must be set to 4 channels ?nmbrchan = 0011?. adc1 cnvtrid (nid = 0x08) [3:0] ch = 2 adc0 cnvtrid (nid = 0x07) [3:0] ch=0 table 7. example channel mapping
idt confidential 21 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo figure 1. multi-channel capture the following figure describes the bus waveform for a 24-bit, 48khz capture stream with id set to 1. figure 2. multi-channel timing diagram adc[1:0] cnvtr bit number sub field name description [15] strmtype stream type (type): 0: pcm 1: non-pcm (not supported) [14] frmtsmplrate sample base rate 0= 48khz 1=44.1khz [13:11] smplratemultp sample base rate multiple 000=48khz/44.1khz or less 001= x2 010= x3 (not supported) 011= x4 192khz only, 176.4 not supported 100-111= reserved [10:8] smplratediv sample base rate divisor 000= divide by 1 001= divide by 2 (not supported) 010= divide by 3 (not supported) 011= divide by 4 (not supported) 100= divide by 5 (not supported) 101= divide by 6 (not supported) 110= divide by 7 (not supported) 111= divide by 8 (not supported) table 8: mult-channel stream id data length adc0 left channel adc0 right channel adc1 left channel adc1 right channel stream id data length adc1 left channel adc1 right channel adc0 left channel adc0 right channel adc0.cnvrtid.channel = 0 adc1.cnvrtid.channel = 2 adc0.cnvrtid.channel = 2 adc1.cnvrtid.channel = 0 0 0 0 sdi bitclk 1 0 0 1 1 0 0 stream id data length stream tag adc0 l23 adc0 l0 adc0 r23 adc0 r0 adc1 l23 adc1 l0 adc1 r23 adc1 r0 left left right right adc0 adc1 data block
idt confidential 22 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 2.14. eapd the eapd pin (pin 47) is a dedicated, bi-direction al control pin. although named external amplifier power down (eapd) by the hd audio specification, this pin operates as an external amplifier power up signal. the eapd value is reflected on the eapd pin; a 1 causes the external amp lifier to power up (equivalent to d0), and a 0 causes it to power down (equivalent to d3.) when the eapd value = 1, the eapd pin must be placed in a state appropriate to the current power state of the associated pin widget even though th e eapd value (in the regist er) may remain 1. the de fault state of this pin is 0 (driving low.) the pin defaults to an open-drain configuration (an external pull-up is recom- mended.) per the hd audio specification and hda015-b, multip le ports may control eapd. the eapd pin assumes the highest power state of all the the eapd bits in all of the pin complexe s. the default value of eapd is 1 (powered on), but the fg po wer state will override and the pin will be low. a port will request external amp po wer up when its power state is active (fg and pin widget power state is d1 or d0) or (analog pc_beep is enabled and port is enabled as an output) and the port?s eapd bit is set to 1. the state of the eapd pin (unless configured as an input or held low by an external circuit when configured as an open dr ain output) will be the logical or of the external amp power up requests from all ports. by default, the eapd pin al so functions as t he mute#/shutdown# input for the internal btl amplifier. in this mode, a low value at the pin (either due to internal eapd being 0, or to an external entity forc- ing the pin low) will cause the intern al btl amplifier to mute or en ter a low power state depending on the amplifier configur ation. (see below) vendor specific verbs are available to configure this pin. these verbs retain their values across link and single function group resets but are set to their default values by a power on reset: [6:4] bitspersmpl bits per sample 000= 8 bits (not supported) 001= 16 bits 010= 20 bits 011= 24 bits 100-111= reserved [3:0] nmbrchan number of channels number of channels for this stream in each ?sample block? of the ?packets? in each ?frame? on the link. 0000=1 channel (not supported) 0001 = 2 channels ? 1111= 16 channels. [7:4] strm software-programmable integer representing link stream id used by the converter widget. by conven- tion stream 0 is reserved as unused. [3:0] ch integer representing lowest channel used by con- verter. 0 and 2 are valid entries if assigned to the same stream, one adc must be assigned a value of 0 and the other adc assigned a value of 2. table 8: mult-channel
idt confidential 23 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo mode1 mode0 eapd pin function description 0 0 open drain i/o value at pin is wired-and of eapd bit and external signal.(default) 0 1 cmos output value of eapd bit in pin widget is forced at pin 1 0 cmos input external signal controls internal amps. eapd bit in pin widget ignored 1 1 cmos input external signal controls internal amps. eapd bit in pin widget ignored table 9. eapd pin mode select control flag description eapd pin mode 1:0 defines if eapd pin is used as in put, output, or bi-direc tional port (open drain) btl/hp sd 0 = amp cont rolled by eapd pin only (default) / 1 = amp controlled by power st ate (pin and fg) only btl/hp sd mode 0 = amp will mute when disabled./ 1 = amp will shut down (enter a low power state) when disabled (default for ya forward) btl/hp sd inv 0 = amp will power down (or mute) when eapd pin is low (default) / 1 = amp will power down (or mute) when eapd pin is high. table 10. control bit descriptions for btl amplifier and headphone amplifier enable configurations btl sd btl sd mode btl sd inv eapd pin state btl amp state 0 0 0 0 amplifier is mute (default 1 ) 1. eapd bit is set to one by default but th e eapd state is 0 after powe r-on reset because t he function group is not in d0. the state after a single or double function group reset will be compliant with hda015-b. 0 0 0 1 amplifier is active 0 0 1 0 amplifier is active 0 0 1 1 amplifier is mute 0 1 0 0 amplifier is in a low power state 0 1 0 1 amplifier is active 0 1 1 0 amplifier is active 0 1 1 1 amplifier is in a low power state 1 0 na na amplifier follows pin/function group power state and will mute when disabled 1 1 na na amplifier follows pin/function group pow er state and will enter a low power state when disabled table 11. btl amp enable configuration hp sd hp sd mode hp sd inv eapd pin state headphone amp state 0 0 0 0 amplifier is mute (default 1 ) 0 0 0 1 amplifier is active 0 0 1 0 amplifier is active 0 0 1 1 amplifier is mute 0 1 0 0 amplifier is in a low power state 0 1 0 1 amplifier is active table 12. headphone amp enable configuration
idt confidential 24 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 0 1 1 0 amplifier is active 0 1 1 1 amplifier is in a low power state 1 0 na na amplifier follows pin/function group power state and will mute when disabled 1 1 na na amplifier follows pin/function group pow er state and will enter a low power state when disabled 1. eapd bit is set to one by default but the eapd state is 0 af ter power-on reset because the function group is not in d0. the state after a single or double function group reset will be compliant with hda015-b. port e headphone amp enable conf iguration bits normal mode aux mode sd (eapd pin or power setting) supported not supported 1 sd inv supported sd mode (power down or mute) supported table 13. port e headphone amp enable configuration support by part and mode 1. sd is ignored in aux mode since the widget power state is ?d3? or ?d3cold?. analog beep enabled eapd pin value 1 1. when pin is enabled as open drain or cmos output. description 0 forced to low when in d2 or d3 follows description in hd audio spec. external amplifier is shut down when pin or function group power state is d2 or d3 independent of value in eapd bit. 1 forced low in d2 or d3 unless port is enabled as output power state is ignored if port is enabled as output and port eapd=1 to allow pc_beep support in d2 and d3 table 14. eapd analog pc_beep behavior afg power state reset# analog pc_beep port power state pin behavior d0-d3 asserted (low) - - active low immediately after po wer on, otherwise the previous state is retained across fg and link reset events d0 de-asserted (high) - - active - pin reflects eapd bit unless held low by external source. d1 de-asserted (high) - d0-d1 active - pin reflects eapd bit unless held low by external source. d2 de-asserted (high) disabled d0-d2 pin forced low to disable external amp d2 de-asserted (high) enabled d0-d2 active - eapd pin high if any port eapd bit =1 and that port also enabled as output. d3 de-asserted (high) disabled d0-d3 pin forced low to disable external amp d3 de-asserted (high) enabled d0-d3 active - eapd pin high if any port eapd bit=1 and that port also enabled as output. d3cold de-asserted (high) - - pin forced low to disable external amp d4 de-asserted (high) - - pin forced low to disable external amp d5 de-asserted (high) - - pin hi-z (off) table 15. eapd behavior hp sd hp sd mode hp sd inv eapd pin state headphone amp state table 12. headphone amp enable configuration
idt confidential 25 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo figure 3. hp eapd example to be replaced by single pin for internal amp figure 4. eapd implementation 2.15. digital microphone support the digital microphone interface permits connection of a digital microphone(s) to the codec via the dmic0, dmic1, and dmic_clk 3-pi n interface. the dmic0 and dmic1 signals are inputs that carry individual channels of digital microphone data to the adc. in the event that a single microphone is used, the data is ported to both adc channels. this mode is selected using a vendor specific verb and the left time slot is copied to the adc left and right inputs. the dmic_clk output is controllable from 4.70 4mhz, 3.528mhz, 2.352mhz, 1.176mhz and is syn- chronous to the internal master cloc k. the default frequency is 2.352mhz. the two dmic data inputs are reported as two st ereo input pin widgets that incorporate a boost amplifier. the pin widgets are shown connected to the adcs through the same multiplexors as the mute + up/down buttons kbc codec spkr amp scan codes os a_sd a_eapd spkr_en# gpio_1 sync from audio gui to kbc sync from kbc to os (mute led on same board) hp audio control block diagram smu mute other external power amp sd# internal btl amp eapd pin control sd/mute codec vdd eapd sd/mute internal headphone amp
idt confidential 26 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo analog ports. although the internal implementation is different between the analog ports and the dig- ital microphones, the functionality is the same. in most cases, the default va lues for the dmic clock rate and data sample phase will be appropriate and an audio driver will be able to configure and use the digital microphones exactly like an analog microphone. to conserve power, the analog portion of the ad c will be turned off if the d-mic input is selected. when switching from the digital microphone to an analog input to the adc, the analog portion of the adc will be brought back to a full power state and allowed to stabilize before switching from the dig- ital microphone to the analog input. this should take less than 10ms. dmic pin widgets support port presence detect directly using sense-b input. the codec supports the following digital microphone configurations: digital mics data sample adc conn. notes 0 n/a n/a no digital microphones 1 single edge 0, or 1 available on either dmic_0 or dmic_1 when using a microphone that supports multiplexed operation (2-mics can share a common data line), configure the microphone fo r ?left? and select mono operation using the vendor specific verb. ?left? d-mic data is used for adc left and right channels. 2 double edge on either dmic_0 or 1 0, or 1 available on either dmic_0 or dmic_1, external logic required to support sampling on a single digital mic pin channel on rising edge and second digital mic right channel on falling edge of dmic_clk for those digita l microphones that don?t support alternative clock edge (multiplexed output) capability. 3 double edge on one dmic pin and single edge on the second dmic pin. 0, or 1 requires both dmic_0 and dmic_1, external logic required to support sampling on a single digital mic pin channel on rising edge and second digital mic right channel on falling edge of dmic_clk for those digita l microphones that don?t support alternative clock edge (multiplexed output) capability. tw o adc units are required to support this configuration 4 double edge 0, or 1 connected to dmic_0 and dmic_1, external logic required to support sampling on a single digital mic pin channel on rising edge and second digital mic right channel on falling edge of dmic_clk for those digita l microphones that don?t support alternative clock edge capability. two adc units are required to support this configuration table 16. valid digital mic configurations power state dmic widget enabled? dmic_clk output dmic_0,1 notes d0 yes clock capable input capable dmic_clk output is enabled when either dmic_0 or dmic_1 input widget is enabled. otherwise, the dmic_clk remains low d1-d3 yes clock disabled input disabled dmic _clk is high-z with weak pull-down d0-d3 no clock disabled input disabled dmic _clk is high-z with weak pull-down d4 - clock disabled input disabled dmic_c lk is high-z with weak pull-down d5 - clock disabled input disabled dmic_c lk is high-z with weak pull-down table 17. dmic_clk and dmic_0,1 operation during power states
idt confidential 27 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo figure 5. single digital microphone (data is ported to both left and right channels dmic_0 or dmic_1 dmic_clk right channel left channel valid data valid data valid data dmic_0 or dmic_1 dmic_clk single line in pin on-chip multiplexer pin digital microphone on-chip off-chip mux stereo channels output stereo adc0 or 1 pcm dmic_0 or dmic_1 dmic_clk left & right channel valid data valid data valid data valid data single ?left? microphone, dmic input set to mono input mode. single microphone not supporting multiplexed output.
idt confidential 28 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo figure 6. stereo digital microphone configuration note: some digital microphone implementations support data on either edge, therefore, the external mux may not be required. dmic_0 or dmic_1 dmic_clk right channel left channel valid data r valid data l valid data r valid data l valid data r digital microphones dmic_clk mux stereo channels output pin pin external multiplexer on-chip multiplexer on-chip off-chip stereo adc0 or 1 pcm mux dmic_0 or dmic_1
idt confidential 29 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo figure 7. quad digital microphone configuration note: some digital microphone implementations support data on either edge, in this case the external multiplexe r is not required. 2.16. analog pc-beep the codec supports automatic routing of the pc_beep pin to port a, port b, and port d outputs when the hd-link is in reset. when the link is active (not held in reset) analog pc-beep may be enabled manually. analog pc_beep is mixed at the por t and only ports enabled as outputs will pass pc_beep. dmic_1 dmic_clk dmic_0 right channel left channel valid data r1 valid data l1 valid data r1 valid data l1 valid data r1 valid data r0 valid data l0 valid data r0 valid data l0 valid data r0 right channel left channel mux stereo channels output for dmic_0 l&r on-chip multiplexer stereo adc0 pcm mux stereo channels output for dmic_1 l&r on-chip multiplexer stereo adc1 pcm digital microphones dmic_clk pin pin external multiplexer mux dmic_0 on-chip off-chip digital microphones pin external multiplexer mux dmic_1
idt confidential 30 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo beep activity monitoring is provided when the an alog beep path is enabled and the codec or ampli- fier is in a low power state (d3). the analog pc beep input is sampled for 500us every 1ms. if the beep input is high or low (>200mvpp) for at least 37% of that time, it is considered active. if it is active for less than 7.5% of that time, it is possibly inactive. if no activi ty is detected for 64ms (128ms, 256ms and 512ms also selectable for the idle threshold), then beep is considered inactive. figure 8. analog pc beep active phase 1: analog beep auto-routing phase in the period af ter application of dvdd, before the first ris- ing edge of link reset. once analog pcbeep is detecte d(beep_presence=1) after 64ms de lays (after por (power on reset)), the amplifier will be turned on(port_pwd= 0, port_output_en=1, there is a timing between these two signals) and analog _beep_en=1. if beep_presence=0 fo r longer than the threshold time, the amplifiers will be turned off to save power and preven t unwanted system noise from being heard. phase 2: when not in phase 1 a. if analog beep function is disabled by driver. analog beep auto- detect will also be disabled. b. if analog beep function is enabled by driver. once analog pcbeep is detected(beep_pres ence=1), analog pc_beep will be enabled if in d0-d2, enabled simply means muting or un-muting beep to avoid hearing system noise on the beep input pin but it is acceptable to turn off port amplifiers if not currently used by dacs, mixer, or beep to save power. if in d3, enabled means that the necessary amplifiers are turned on so that the beep signal may be heard on all ports configured as outputs (see analog pc-beep description section above) all needed amplifiers ar e enabled until beep_presence=0 for longer than the idle threshold a flow chart of analog pc beep is below.
idt confidential 31 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo figure 9. analog pc beep flow chart 2.17. digital pc-beep this block uses an 8-bit divider value to generate the pc beep from the 48khz hd audio sync pulse. the digital pc_beep block generates the beep tone on all pin complexes that are currently configured as outputs. the hd audio spec states that the beep tone frequency = (48khz hd audio por wait 64ms activity on pin? link reset active? turn on amplifiers / enable beep path activity on pin? no analog pc_beep enabled? yes yes yes yes activity on pin? inactivity over threshold? disable beep path / turn off amplifiers no yes no no no idle no no
idt confidential 32 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo sync rate) / (4*divider), producing tones from 47 hz to 12 khz (logarithmic scale). other audio sources are disabled when digital pc_beep is active. it should be noted that digital pc be ep is disabled if the divider = 00h. pc-beep may be attenuated and distorted when the codec is in d3 depending on the load imped- ance seen by the output amplifier since all port s are in a low power state while in d3. load imped- ances of 10k or larger can supp ort full scale outputs but lower impedance loads will distort unless the output amplitude is reduced. digital pc_beep requires a clock to operate and the codec will prevent the system from stopping the bus clock wh ile in d3 by setting the clock_stop_ok bit to 0 to indicate that the part requires a clock. 2.18. headphone drivers the codec implements both traditional and capless headphone outputs. the microsoft windows logo program allows up to the equivalent of 100ohms in series. however, an output level of +3dbv at the pin is required to support 300mv at the jack with a 32ohm load and 1v with a 320 ohm load. microsoft allows device and system manufactures to limit output voltages to address eu safety requirements. (wlp 3.09 - please refer to the latest windows logo program requirements from microsoft.) the codec does not support power limiting. headphone performance will degr ade if more than one port is driving a 32 ohm load. 2.19. btl amplifier an integrated class-d stereo btl amplifier is pr ovided to directly drive 4 ohm speakers (2w @ 4.75v) or 8 ohm speakers (1w @ 4.75v). no external filter is needed for cable runs of 18? or less. an internal dc blocking filter prevents distorti on when the audio source has dc content, and pre- vents unintentional power consumption when paus ing audio playback. the amplifier may be con- trolled using the eapd pi n (see eapd section.) using a vendor specific verb, the btl amplifier may be configured to support a mono speaker con- nected to the l +/- pins. in this mode, the left a nd right audio is mixed and sent to the left output only. the right channel is turned off to conserve power. maximum gain for the btl amplifier is programmab le. the following 4 gain se ttings relative to a nominal line output are desired: +6.5db, +9.5db, +14.5db, +16.5db. absolute gain may vary and the suggested accura cy is +/-1.5db. this gain is exposed in a vendor specific widge t and is intended to mimic the pin programmable gain implemented in discrete btl amplifiers commonly used in notebook computers. the btl amplifier includes thermal management circuitry. when the codec reaches a temperature of about 140 degrees, the output amplitude of the btl amp is gradually lowered until the tempera- ture falls below 140. all other functions will remain active if the btl amplifier is shut down due to die temperature. 2.20. btl amplifie r high-pass filter for mobile applications, speakers are often in capable of reproducing low frequency audio and unable to handle the maximum output power of th e btl amplifier. a high-pass filter is implemented in the btl output path to reduce the amount of lo w frequency energy reaching speakers attached to the btl amplifier. this can prevent speaker failure.
idt confidential 33 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 2.20.1. filter description the high-pass filter is derived from the common biqu adratic filter and provides a 12db/octave roll-off. the filter may be programmed for a -3db response at: 100hz, 200hz, 300hz , 400hz, 500hz, 750hz, 1khz, or 2khz. the high pass filter is enabled by default with a cut-off frequen cy of 300hz. the filter may be bypassed using the associat ed verb (processi ng state verb). the analog pc_beep input is not affected by the digi tal high-pass filter. to ensure that the speakers attached to the btl amplifier are not harmed by low frequency audio entering the pc_beep input, an external filter must be implemented. fortunately, it is common practice to implement an attenuation circuit and dc blocking capacitor at the pc_beep input. this attenuator/filter is easily adjusted to restrict low frequency audio. the easiest approach is to reduce the value of the dc blocking capaci- tor but other approaches are equally effective. 2.21. eq there are 5 bands of parametric eq (bi-quad) per channel. due to th e flexibility of th e bi-quad imple- mentation, each filter band may be configured as a high-pass, low-pass, band-pass, high shelving, low shelving, or other function. each band has an independent set of coefficients. a bi-quad filter has 6 coefficients. one coefficient is normalized to 1 and 5 are programmed into the core. each band supports up to +15db boost or up to -36db cut. 2.22. combo jack detection 4 conductor (combo) jacks are becoming popular. in the most common implementation the 4 con- ductor plug has the same mechanical dimensions as a 3 conductor 3.5mm plug but the sleeve por- tion has been split into two segments:s1 and s2. wh en a 4-conductor plug (headset) is inserted into the jack t (tip) = left headphone audio, r (ring) = right headphone audio, s1 (first half of sleeve) = microphone input, and s2 (second half of sleeve) = return (gnd). when a 3-conductor plug (headphones) is inserted into the jack; t=left audio, r=right audio, s1 =gnd, s2=gnd. by moni- toring the s1 connection to see if it is shorted to ground, we can distinguish between headsets and headphones. please note that analog microphone plugs (3-conductor-lmic/rmic/gnd) and optical spdif plugs can not be support ed using this implementation. figure 10. combo jack plug insertion is reported on the headphone po rt using the switch in tegrated into the jack. the internal circuit monitors the voltage at the jack to determine if a low impedance load is present. g n d mi c
idt confidential 34 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo detection of a microphone is not reported unless plug insertion is also detected. 2.23. gpio 2.23.1. gpio pin mapping and shared functions 2.23.2. spdif/digital microphone/gpio selection 3 functions are available on the dmic_1/gpio0/spdifout1 pin (pin 46). to determine which func- tion is enabled, the order of precedence is followed: 1. if the gpios are enabled, they over ride both spdif_out and digital mics 2. if the gpios are not enabled through the afg, then at reset, the pin is pulled low by an internal pull-down resistor. 3. if the port is en abled as an input, the di gital microphones will be used. 4. if the port is enable d as an output, the spd if output will be used. 5. in the event that the port is enabled as an in put and an output, the port will be an output and the digital mic path will be mute. 2.23.3. digital microphone/gpio selection 2 functions are available on the dmic_clk/gpio1 (pin 2) and the dmic_0/gpio2 (pin 4) pins. to determine which function is enabled, the order of precedence is followed: 1. if gpios are not enabled through the afg, then at reset, pins 2 and 4 are pulled low by an inter- nal pull-down resistor. 2. if the gpio 1 is enabled, the 2 dmic pins become mute (unless programmed for gpio or spdif use) and pin 2 becomes gpio with an internal pull-down. 3. if gpio2 is enabled through the afg, pin 4 becomes a gpio and is pulled low by an internal pull-down resistor. 4. if the port is en abled as an input, the di gital microphones will be used. 5. if the port is not enabled as an input or if the pin is configured as a gpio, the digital microphone path will be mute. 2.24. hd audio hda015-b support the codec provides complete su pport for the hda015-b specification (now dcn) building on the support already present in previous prod ucts. hda015-b features supported are: 1. persistence of many configuration options through bus and function group reset. 2. the ability to support port presen ce detect in d3 even when the hd audio bus is in a low power state (no clock.) gpio # pin supply spdif in spdif out gpi/o gpi gpo vrefout dmic vol pull up pull down 0 46 dvdd yes yes in 50k 1 2 dvdd yes clk 50k 2 4 dvdd yes in 50k 3 48 dvdd yes yes 50k 4 24 avdd yes yes 50k
idt confidential 35 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 3. fast resume times from low power states: 1m s d1 to d0, 2ms d2 to d0, 10ms d3 to d0. 4. notification if persistent register settings have been unexpectedly reset. 5. spdif active in d3 (required) 2.25. digital core voltage regulator the digital core operates from a 1.8v (10%) supp ly voltage. many systems require that the codec use a single 3.3v digital supply, so an integrated regulator is included on die. the regulator uses pin 9, dvdd, as its voltage source. the output of the ldo is connected to pin 1 and the digital core. a 10uf capacitor must be placed on pin 1 for proper load regulation and regulator stability. the digital core voltage regulator is only dependent on dvdd. dvddio may be either 3.3 or 1.5v and may precede or follow dvdd in sequence. the codec digital logic and i/o (unless referenced to avdd) will operate in the absen ce of avdd. dvdd and avdd supp ly sequencing for the applica- tion of power and the removal of power is neither defined nor guaranteed. it is common for desktop systems to supply avdd from the system standb y supply and the codec will tolerate, indefinitely, the condition where avdd is active but dvdd and dvddio are inactive.
idt confidential 36 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 2.26. digital audio port (i2s) digital input and output capability is provided on port f and port e.. 2.26.1. characteristics i2s output is represented as an output port with a headphone output amplifier. i2s input is repre- sented as an input port. to ensure compatibility with the microsof t class driver, the port is described as an analog port and provides the same connectivity as a traditional analog port. the i2s ports share common clocks. therefore only one set of configuration controls are required. 2 stereo analog ports are replaced by the data input(i2s_din), data output(i2s_dout), data clock(i2s_sclk), and frame clock (i2s_lrclk) signals. due to the requirement that input and output conv erters provide independent sample rates, sample rate conversion support is provided. multiple data formats are supported: left justified, i2s native (left justified with 1 clock delay), and right justified modes. data length s of 16, 20 and 24 bits are supported. when there is a mismatch between the i2s configuration and the hd audio link programming (converter widget word length) the word lengths will be a ligned using zero padding or truncation as appropriate. the codec may be the clock master or a slave to an external master for the shift clock (sclk) and frame clock (lrclk) signals. data shift clock is programmable with a default providing 64 fs for 44.1khz based rates and 84fs for 48khz based rates. a 64fs shift clock is also available for 48khz rates but the jitter performance will be much worse than 84fs. by def ault, the shift clock will automa tically adjust for sample rate. however, the shift clock may also be programmed to provide a constant output independent of the selected sample rate. sclk[3:0] frequency (mhz) pll clock divisor suggested sample rate 1 clocks/fr ame notes 0000 auto auto all 64 sclk is always 64fs (48khz based rates have jitter) 0001 12.288 147/16 192khz 64 high jitter (<5ns) 0010 6.144 147/8 96khz 64 high jitter (<5ns) 0011 3.072 147/4 48khz 64 high jitter (<5ns) 0100 11.2896 10 88.2khz 128 0101 5.6448 20 88.2khz 64 0110 2.8224 40 44.1khz 64 0111 reserved 1000 auto auto all 64/84 sclk adjusts for sample rate. 44.1khz based rates are 64fs and 48khz based rates are 84fs 1001 16.128 7 192khz 84 1010 8.064 14 96khz 84 1011 4.032 28 48khz 84 table 18. sclk frequency selection
idt confidential 37 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo it is possible to invert all clocks (shift, master, and lr clocks) as well as the port f data input and port e data output. the 92hd93 inverts the clocks and data by default. ports are enabled/disabled using the input / output enables defined in the pin widgets. aux audio mode will be supported and the codec will us e the mclk pin as an input in this mode. a 12mhz input will be accepted. (see the aux audio section for more information.) in normal operation, the mclk pin is an output by default but may be configured as an intput . 8 clock frequencies are available: 22.5792mhz (512x 44.1k), 11.2896mhz (2 56x 44.1khz), 5.6448mhz (128x 44.1khz), 28.224mhz (640x 44.1khz), 14.112mhz (320x 44.1khz), 7.056mhz (160x 44.1khz), 24mhz (500x 48khz), and 12mhz (250x 48khz - default) a ?bit exact mode? is provided. in this mode, the output path will no t alter the data from the dac con- verter widget (hd audio stream data) sent to the i2s output port (port e.) this means that there is no sample rate conversion, rounding , filtering or other processing that will change the sample value. word length and sample rate are determined by the converter widget connected to the output port and not by the i2s rate and word length configuration bits. the in put port (if used) will have its rate and word length converted to the requested rate of the adc converter widget attached to the input port. the input path may be bit exact if the dac and adc converter widgets are programmed to the same rates and word lengths. 1100 7.056 16 88.2khz 80 1101 3.528 32 44.1khz 80 1110 1.764 64 44.1khz 40 1111 reserved 1.in ?auto? mode sclk is referenced to the sample rate (s r[2:0] register bits) but in a ll other settigns the sclk rate is independent of the selected sample rate. programming a sample rate that uses a different base rate from the suggested sample rate may cause corruption of the audio stream. mclk[2:0] frequency (mhz) pll clock divisor suggested sample rate notes 000 24 na 96khz hd audio bitclk 001 12 na 48khz hd audio bitclk/2 010 22.5792 5 88.2khz 011 11.2896 10 44.1khz 100 5.6448 20 44.1khz 101 28.224 4 88.2/96khz 110 14.112 8 88.2/48khz 111 7.056 16 44.1khz table 19. mclk frequency selection sclk[3:0] frequency (mhz) pll clock divisor suggested sample rate 1 clocks/fr ame notes table 18. sclk frequency selection
idt confidential 38 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 2.26.2. left justified audio interface in left justified mode, the msb is available on the first rising edge of sclk following a lrclk tran- sition. the other bits are then transmitted in orde r. the lrclk signal is high when left channel data is present and low when right channel data is present. figure 11. left justified audio interface (assuming 24-bit word length) 2.26.3. right justified audio interface (assuming n-bit word length) in right justified mode, the lsb is available on th e last rising edge of sclk before a lrclk transi- tion. all other bits are transmitted in order. the lrclk signal is high when left channel data is pres- ent and low when right channel data is present. figure 12. right justified audio interface (assuming 24-bit word length) 2.26.4. i 2 s format audio interface in i 2 s mode, the msb is available on the second risi ng edge of sclk following a lrclk transition. the other bits up to the lsb ar e then transmitted in order. figure 13. i 2 s justified audio interface (assuming 24-bit word length) 2.27. microphone mute input the 92hd93 supports a microphone mute input. an external switch or other circuit may directly mute the codec without rely ing on software control. this is a most helpful feature for allowing the sclk lrclk l23 l21 l22 l20 l19 l17 l18 l16 l15 l13 l14 l12 l11 l09 l10 l08 l07 l05 l06 l04 l03 l01 l02 l00 r23 r21 r22 r20 0 r19 r17 r18 r16 r15 r13 r14 previous sample dout / din left channel right channel word length (wl) left justified fs/2 sclk lrclk l23 l21 l22 l20 l19 l17 l18 l16 l15 l13 l14 l12 l11 l09 l10 l08 l07 l05 l06 l04 l03 l01 l02 l00 r23 r21 r22 0 previous sample dout / din left channel right channel word length (wl) right justified 0 fs/2 sclk lrclk l23 l21 l22 l20 l19 l17 l18 l16 l15 l13 l14 l12 l11 l09 l10 l08 l07 l05 l06 l04 l03 l01 l02 l00 r23 r21 r22 r20 0 r19 r17 r18 r16 r15 r13 r14 previous sample dout / din left channel right channel word length (wl) i2s fs/2
idt confidential 39 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo end user to conveniently enforce privacy since it bypasses the record gain/mute functions typiclaly controlled by software. while re cording is muted, any active st ream will receive digital silence.
idt? confidential 40 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 2.28. aux audio support the codec supports an auxiliary au dio mode where audio routing is suppor ted by default after power is supplied with the hd audio bus disabled. in this mode, an i2s input is routed to one of sev- eral output ports depending on jack presence detection, likewise seceral audio sources (analog, dig- inal mic, i2s) are routed and converted to an i2s output. in addition to shutting of the codec btl and headphone amplifiers when the dock output jack is used, the btl amplifier will be disabled when th e headphone jacks are us ed, and the headphone amplifiers will be disabled when not in use. 2.28.1. general conditions in aux audio mode: hd audio link is off (rst# is 0, active, and bitclk is 0, inactive. codec does not need to monitor bitclk to enter/exit this mode but must not depend on bitclk to operate.) (p art will enter aux audio mode immediately on application of power if aux audio mode is enabled as default.) or hd audio codec function group power state is set to d3cold and aux audio mode is enabled. (device enters immediately on transition to d3cold and remains in aux mode until a double afg reset event is received or unt il the next rising edge of rst#) ? hd audio codec analog and digital supplies are active. ? port a connects to the system microphone jack. ? port b connects to the system headphone jack. ? port c is not used ? port d connects to the internal speakers. ? port e is connected to the dock line out jack/aux audio out (it is an output port) ? port f is connected to the dock mic input jack/aux audio in (it is an input port) ? the digital microphone clock is generated by the codec. the dmic data is converted to pcm and sent to the aux audio module through the aux out port. ? the system microphone jack (por t a) is available to the auxilia ry audio subsystem. vref_out will be enabled when the system mic is plugged in. ? eapd is used to control the po wer state of the mixer, btl amp lifier, and headp hone amplifiers. the amplifiers are off if eapd is held low. ? internal circuitry will delay enab ling (change power state, un-mute, etc.) the output amplifiers a sufficient amount of time after the application of powe r or eapd=1 to prevent pops. ? internal circuitry will orch estrate power down (eapd = 0) to prevent pops. ? eapd must be forced lo w before removing power. ? no special dock signal present for the codec. only port presence detect for the dock line out (port e) and minin (poer f) are used. ? ecr15b operation does not presents a problem. the codec will not enter aux audio mode unless the function group power state is set to d3cold prior to putting the hd audio interface into reset (controller d3.)to prevent undesirable behav ior (pops, etc.) the bus must not be placed into reset with the clock stopped unless eapd is fo rced low or d3cold ha s been set. the enable bit in the aux audio vendor specific verb is prov ided so firmware or other software can disable aux audio support. the default value of this bit is determined by a bond option and may be determined by reading the device id. this bit onl y returns to its default value when a power on reset event is generated or when programmed to that value by software.
idt? confidential 41 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 2.28.2. entering aux audio mode enter aux mode under two conditions, refer to figure below: ? when dvdd is powered-up, the value of aux_enable register is ?enabled? (one), and before link reset is de-asse rted (pull high). ? if aux_enable is ?enabled? (one ) and the power state is d3cold then chip will also enter aux mode but the clock_sto p_ok flag is not required (set to 1 if convenient.). (note that the part will enter aux mode immediately upon transition to d3cold. it is possible to return to normal opera- tion by issuing a do uble afg reset if t he link is still active.) note: at that time, force portsense and btl amp on when we enter link rese t if the auxaudio bit is set. if the auxaudio bit is not set (by bond option or software ) then we will not enter aux audio mode-portsense and bt l amp will remain off. port f (?dock microphone?) input is routed to po rt d (?internal speakers?), ports b (system head- phone port), and port e (?dock line out?) directly. t he analog mixer is disabled to reduce power con- sumption. figure 14. switching between normal and aux audio modes 2.28.3. firmware/software requirements: the reconfiguration out lined in this chapter will be enabled by default (without the help of firmware or os driver.) dvdd dig_por link_reset aux_enable (register) aux_mode operation mode normal mode d3 power state d0 d3 d3 with clock d3 clockless d0 d3 cold normal mode aux_mode
idt? confidential 42 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo if it is desirable to stop the hd audio bus while th e codec is in d3 under os control per ecr-15b, no action is required . the codec will not enter aux audio mode unless placed in d3cold. 2.28.4. part options supporting i 2 s i/o ports e and f are implemented using an i 2 s digital interface. the spdif pins (pins 46 and 48) are used to connect to an external aux audio module. the codec is a lr_clk and s_clk clock slave to the external module, if present, and is the timing master in normal mode. the codec is an mclk slave by default in both aux audio and normal modes. the internal routing of the playback and record pa ths are functionally similar to an analog implemen- tation but must be processed differently because th e audio data is now digital. in addition, the pc_beep pin is replaced by a secondary i2s data input that is used in both aux audio and normal modes of operation. the fo llowing diagrams illustrate. 2.28.5. ?playback path? port behavior (digital i/o) input from the aux audio module (aux_in) is routed to port d (?internal speakers?), port b (system headphone port), and port e (?dock line out?) dire ctly. the secondary audio input is mixed with the aux_in input. 2.28.6. when port e presence detect = 0 ? presence detect for port e = 0 (nothing plugged in) ? aux_in, the ?aux audio playback?, input is mi xed with the secondary audio input and routed to port b, or port d when that port is active. ? if port b is in use (port presence detect = 1), port d, internal speakers, will be in active (off) and port e, the dock headphone, will be mute. ? the power supply (charge pump) for b will be inactive if b is not in use. ? if port b is not in use (port pres ence detect = 0), port d, internal speakers, will be active and port b will be inactive. ? eapd must not be forced low due to the dock being absent or high w hen a dock is present. eapd is used to indicate if aux audio mode is in use. 2.28.7. when port e presence detect = 1 ? presence detect for port e = 1 (something plugged in) ? port d is disabled ? if port b is in use (port presence detect = 1), th at port will be enabled an d output the audio enter- ing aux_in mixed with the audio on the secondary audio input. ? the power supply for port b will be active if port b is in use. ? if port b is not in use (port presence detect = 0), port b will be inactive and the audio on aux_in will be mixed with the audio from the secondary audio input and routed to port e, the dock headphone jack. ? eapd must not be forced low due to the dock being absent or high w hen a dock is present. eapd is used to indicate if aux audio mode is in use.
idt? confidential 43 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 2.28.8. ?record path? port behavior (digital i/o) digital microphone input dmic0 is used as an internal microphone port in normal mode. the digital microphone clock pin is enabled in aux audio mo de and the digital microphone clock is provided by an internal oscillator. the data on the dmic0 pin is converted to pcm data and sent to the auxiliary audio module. if port f and port a presence detect = 0, this indi cates that nothing is plugged into the dock or sys- tem and the digital micro phone input is sent to th e auxiliary audio module. if port a presence detect = 1, this indicates that an exte rnal microphone is plu gged into the system ja ck and port a is con- verted to pcm data and se nt to the auxiliary audio module through the aux_ou t pin. if port f pres- ence detect = 1 (and port a presence detect = 0), this indicates that an external microphone is plugged into the dock. th e pcm data from port f will be rout ed to the auxiliary audio module through the aux_out pin. as in normal mode, the boost and record gain functions are available in aux audio mode for port a and dmic0. eapd (pin) aux support enable 1 1.default value for aux audio enable is determined by bond option. port e detect port b detect port a, c, f, dmic detect port d behavior port b behavior port e behavior 0 na na na na disabled disabled disabled (mute) 1 0 na na na widget controlled widget controlled widget controlled 11 00 na enabled aux+secondary disabled disabled (mute) 1 1 0 1 na disabled enabled aux+secondary disabled (mute) 1 1 1 0 na disabled disabled enabled aux+secondary 1 1 1 1 na disabled enabled aux+secondary disabled (mute) eapd (pin) aux support enable 1 1.default value for aux audio enable is determined by bond option. d mic0 detect port a detect port f detect ports b, c, e detect port e behavior 0 x x x x na disabled 1 0 x x x na widget controlled 1 1 000 na mute 1 1 100 na dmic converted to analog and routed to module through port e. dmic clock provided by codec 11x01 na dock mic routed to module (not through codec) codec dmic interface and port a disabled
idt? confidential 44 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 2.28.9. eapd since the aux audio mode overrides the default b ehavior but not the actual port settings when in reset, the logical state of the eapd pin must be overridden as well. when aux audio mode is enabled and the part is in reset as described ab ove, the logical state of eapd will be 1 (external amplifier powered up) unless held low by an external circuit. this ensures that audio pass-thru and analog pc_beep will be supported. 2.28.10. class-d btl issues while in aux audio mode the hd audio bus clock (bitclk) is not availabl e. the class-d controller requires a very high speed clock to operate and an internal clock must be provided. in aux audio mode, the actual fr equency used by the class-d controller an d its associated adc will not be exact since an external referenc e will not be available.the performance characteristics in aux audio mode will be degraded compared to the normal operating mode c haracteristics specified elsewhere in this document. 2.28.11. firmware/software requirements: the reconfiguration outlined in this chapter is autonomous (without the help of firmware or os driver.) this autonomous mode does not interfere with normal operation. if it is desirable to stop the hd audio bus while the codec is in d3 under os control per dcn hda015-b, no action is required. the codec w ill not enter aux audio mode unless placed in d3cold.
idt? confidential 45 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 2.28.12. system diagrams figure 15. playback path on parts supporting digital i/o dac adc a b e f dm d c hp spkr na mic d-mic hd audio interface dock hp mic mo mi aux audio module ec ei eq s dac adc a b e f dm d c hp spkr na mic d-mic hd audio interface dock hp mic mo mi aux audio module ec ei eq s dac adc a b e f dm d c hp spkr na mic d-mic hd audio interface dock hp mic mo mi aux audio module ec ei eq s aux audio mode playback speaker playback headphone playback dock headphone
idt? confidential 46 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo figure 16. record path on parts supporting digital i/o dac adc a b e f dm d c hp spkr na mic d-mic hd audio interface dock hp mic mo mi aux audio module ec ei eq s dac adc a b e f dm d c hp spkr na mic d-mic hd audio interface dock hp mic mo mi aux audio module ec ei eq s dac adc a b e f dm d c hp spkr na mic d-mic hd audio interface dock hp mic mo mi aux audio module ec ei eq s aux audio mode record digital mic record analog mic record dock mic
idt? confidential 47 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 2.28.13. i2c control interface the codec supports i2s i/o also supports a 2-wire (i2c and smbus compatible)8-bit slave inter- face for control while in aux audio mode. the interface supports up to 400khz operation. the following must be contro lled while in aux audio mode: 6. eq programming 7. btl amplifier high-pass filter programming 8. mono out path band-pass filter programming 9. btl amplifier gain 10. port a mic boost and adc record gain 11. dmic0 boost and adc record gain 2.28.14. register write cycle the controller indicates the start of data transfer with a high to low transition on sda while scl remains high, signalling that a device address and data will follow. all devices on the 2-wire bus respond to the start condition and shift in the next eight bits on sda (7-bit address + read/write bit, msb first). if the device address received matches the address of the codec and the r/w bit is ?0?, indicating a write, then the codec responds by pulling sda low on the next clock pulse (ack); other- wise, the codec returns to the idle condition to wait for a new start cond ition and valid address. once the codec has acknowledged a correct address, the controller sends the register address. the codec acknowledges the register address by pulling sda low for one clock pulse. the controller then sends the 8 bits of register data and the codec acknowledges again by pulling sda low. when there is a low to high transition on sda while scl is high, the transfer is complete. after receiving a complete address and data sequence the codec returns to the idle state. if a start or stop condition is detected out of sequence, the device returns to the idle condition. figure 17. 2-wire serial control interface 2.28.15. multiple write cycle the controller may write more than one register within a single write cycle. to write additional regis- ters, the controller will not generate a stop or star t (repeated start) command after receiving the acknowledge for the data payload. instead the co ntroller will repeat sending 8- bit data payloads. the register address will increm ent automatically after receiving each 8-bit payload. scl sda device address da[6:0] r/ nw start ack register address ra[7:0] register data rd[7:0] ack ack stop
idt? confidential 48 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo figure 18. multiple write cycle 2.29. register read cycle the controller indicates the start of data transfer with a high to low transition on sda while scl remains high, signalling that a device address and data will follow. if the device address received matches the address of the codec and the r/w bit is ?0?, indicating a write, then the codec responds by pulling sda low on the next clock pulse (ack); ot herwise, the codec returns to the idle condition to wait for a new start condition and valid address. once the codec has acknowledged a correct address, the controller sends a restart command (high to low transition on sda while sc l remains high). the controller then re-sends the devices address with the r/w bit set to ?1? to in dicate a read cycle.the codec a cknowledges by pulling sda low for one clock pulse. the controller then receives a byte of register data and the controller acknowledges by pulling sda low. when there is a not acknowledge from the controller and a low to high transition on sda while scl is high, the transfer is complete. if a start or st op condition is detected out of sequence, the device returns to the idle condition. figure 19. read cycle 2.29.1. multiple read cycle the controller may read more than one register withi n a single read cycle. to read additional regis- ters, the controller will not genera te a stop or start (repeated st art) command af ter sending the acknowledge for the second byte of data. instead the controller w ill continue to provide clocks and acknowledge after each byte of transmitted data. the codec will aut omatically increment the internal register address after each register has had its da ta successfully read (ack from host) but will not increment the register address if the data is not re ceived correctly by the host (nack from host) or if the bus cycle is terminat ed unexpectedly (however the eq/filter addres s will be incremented even if the register address is not incremented when performing eq/filter ram reads). scl sda device address da[6:0] r/ nw start ack register address ra[7:0] register data rd[7:0] ack ack stop ack ack register write 1 register write 2 ... register data rd[7:0] @ra[7:0]+1 register write n register data rd[7:0] @ra[7:0]+n scl sda device address da[6:0] r/ nw start ack register address ra[7:0] register data rd[7:0] ack stop nack device address da[6:0] r ack restart
idt? confidential 49 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo figure 20. multiple read cycle 2.29.2. i2c registers the codec that supports i2s i/o also supports a 2-wire (i2c and smbus compatible) interface for control while in aux audio mode. the interface supports up to 400khz operation. all registers (except for the reset register) are available when in normal mode through the hd audio interface. most are implemented using vendor defined verbs but some (volume controls specifically) are sup- ported through standard verbs at the pin widgets. register name remarks bit[7] bit[6] bi t[5] bit[4] bit[3] bit[2] bit[1] bit[0] defa ult r0(00h) rsvd reserved r1(01h) spkvoll spkr left volume spkvol_l[7:0] 30h r2(02h) spkvol r spkr right volume spkvol_r[7:0] 30h r3(03h) rsvd reserved r4(04h) rsvd reserved r5(05h) rsvd reserved r6(06h) aic1 audio interface 1 sclkin v ms lrswa p lrp wl[1:0] format[1:0] 4ah r7(07h) aic2 audio interface 2 tri sclk[3:0] sr[2:0] 04h r8(08h) aic3 audio interface 3 mclkm s mclk[2:0] 09h r9(09h) pwrm pwr mgmt hppwd spkrp wd dmicp wd mclko ut auxen 03h r10(0ah) r11(0bh) r12(0ch) r13(0dh) r14(0eh) r15(0fh) reset reset writing to th is register resets all regi sters to their default state 00h not reset r16(10h) status btl status limit1lat ch limit0lat ch limit1 limit0 zerodet _flag 00h r17(11h) init anabee p_dc byp anabee p_dc coeff1 anabee p_dc coeff0 initialize 04h r18(12h) config1 config1 bpf byp pre byp eqbyp hpf byp 60h table 20. i2c registers da[6:0] nw ack ra[7:0] rd[7:0] ack ack nack da[6:0] r ack sr s p set register address read register @ ra[7:0] rd[7:0] read register @ ra[7:0] + 1 ack rd[7:0] read register @ ra[7:0] + n
idt? confidential 50 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo r19(13h) pwm4 sc_statu s_clear _right sc_statu s_clear _left rsvd sc_faul t_status _right sc_faul t_status _left scdly_ sel1 scdly_ sel0 evenbit 00h r20(14h) pwm3 outctrl1 outctrl0 cvalue5 cvalue4 cvalue3 cvalue2 cvalue1 cvalue0 02h r21(15h) pwm2 dvalue5 dvalue4 dvalue3 dvalue2 dvalue1 dvalue0 pwm_o utflip pwm_o utmode 41h r22(16h) pwm1 ditherpo s4 ditherpo s3 ditherpo s2 ditherpo s1 ditherpo s0 dither_r ange dithclr 00h r23(17h) pwm0 ph_offs et1 ph_offs et0 clk320m ode roundup bfclr fourthor der add3_s el btl_test _mode 70h r24(18h) lmtctrl lzcen limitste p1 limitste p0 limiter_ en 00h r25(19h) lmtatktime atk10 m lmtat6 lmtat5 lmtat4 lmtat3 lmtat2 lmtat1 lmtat0 00h r26(1ah) lmtholdtime hold1 0m lmtht 6 lmtht 5 lmtht 4 lmtht 3 lmtht 2 lmtht 1 lmtht 0 00h r27(1bh) lmtreltime rel10 m lmtrt 6 lmtrt 5 lmtrt 4 lmtrt 3 lmtrt 2 lmtrt 1 lmtrt 0 00h r28(1ch) lmtatkth_hi latkt h15 latkt h14 latkt h13 latkt h12 latkt h11 latkt h10 latkt h9 latkt h8 7fh r29(1dh) lmtatkth_lo latkt h7 latkt h6 latkt h5 latkt h4 latkt h3 latkt h2 latkt h1 latkt h0 ffh r30(1eh) lmtrelth_hi lrelt h15 lrelt h14 lrelt h13 lrelt h12 lrelt h11 lrelt h10 lrelt h9 lrelt h8 00h r31(1fh) lmtrelth_lo lrelt h7 lrelt h6 lrelt h5 lrelt h4 lrelt h3 lrelt h2 lrelt h1 lrelt h0 00h r32(20h) gainctrl_hi zerodetl en1 zerodetl en0 step_ti me2 step_ti me1 step_ti me0 15h r33(21h) gainctrl_lo clr_latch step_10 ms stepped _chang e disable_ gain auto_m ute change _mode mute_m ode 05h r34(22h) mute mute mute1 mute0 00h r35(23h) atten atten7 atten6 atten5 at ten4 atten3 atten2 atten1 atten0 00h r36(24h) dc_coef_sel dc_coef _sel2 dc_coef _sel1 dc_coef _sel0 05h r37(25h) hpf_coef_sel hp_coef _sel2 hp_coef _sel1 hp_coef _sel0 02h r38(26h) bpf_coef_sel bph_co ef_sel2 bph_co ef_sel1 bph_co ef_sel0 bpl_coe f_sel2 bpl_coe f_sel1 bpl_coe f_sel0 32h r39(27h) pwr stage test left enable trc_e sd stren drv scthr _1 scthr _0 deadti me2 deadti me1 deadti me0 89h r40(28h) short circuit test left test_ en sc_dis fault_ sc pnsel force_ sc test 00h r41(29h) pwr stage test right enable trc_e sd stren drv scthr _1 scthr _0 deadti me2 deadti me1 deadti me0 89h r42(2ah) short circuit test right test_ en sc_dis fault_ sc pnsel force_ sc test 00h register name remarks bit[7] bit[6] bi t[5] bit[4] bit[3] bit[2] bit[1] bit[0] defa ult table 20. i2c registers
idt? confidential 51 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo r43(2bh) ldo level control lv_qu ad_bia s lv_reg_ cntrl_bit 1 lv_reg_ cntrl_bit 0 00h r44(2ch) r45(2dh) r46(2eh) r47(2fh) r48(30h) eqram_read[47:40] eqrd4 7 eqrd4 6 eqrd4 5 eqrd4 4 eqrd4 3 eqrd4 2 eqrd4 1 eqrd4 0 00h r49(31h) eqram_read[39:32] eqrd3 9 eqrd3 8 eqrd3 7 eqrd3 6 eqrd3 5 eqrd3 4 eqrd3 3 eqrd3 2 00h r50(32h) eqram_read[31:24] eqrd3 1 eqrd3 0 eqrd2 9 eqrd2 8 eqrd2 7 eqrd2 6 eqrd2 5 eqrd2 4 00h r51(33h) eqram_read[23:16] eqrd2 3 eqrd2 2 eqrd2 1 eqrd2 0 eqrd1 9 eqrd1 8 eqrd1 7 eqrd1 6 00h r52(34h) eqram_read[15:08] eqrd1 5 eqrd1 4 eqrd1 3 eqrd1 2 eqrd1 1 eqrd1 0 eqrd0 9 eqrd0 8 00h r53(35h) eqram_read[07:00] eqrd0 7 eqrd0 6 eqrd0 5 eqrd0 4 eqrd0 3 eqrd0 2 eqrd0 1 eqrd0 0 00h r54(36h) eqram_write[47:40] eqwd4 7 eqwd4 6 eqwd4 5 eqwd4 4 eqwd4 3 eqwd4 2 eqwd4 1 eqwd4 0 00h r55(37h) eqram_write[39:32] eqwd3 9 eqwd3 8 eqwd3 7 eqwd3 6 eqwd3 5 eqwd3 4 eqwd3 3 eqwd3 2 00h r56(38h) eqram_write[31:24] eqwd3 1 eqwd3 0 eqwd2 9 eqwd2 8 eqwd2 7 eqwd2 6 eqwd2 5 eqwd2 4 00h r57(39h) eqram_write[23:16] eqwd2 3 eqwd2 2 eqwd2 1 eqwd2 0 eqwd1 9 eqwd1 8 eqwd1 7 eqwd1 6 00h r58(3ah) eqram_write[15:08] eqwd1 5 eqwd1 4 eqwd1 3 eqwd1 2 eqwd1 1 eqwd1 0 eqwd0 9 eqwd0 8 00h r59(3bh) eqram_write[07:00] eqwd0 7 eqwd0 6 eqwd0 5 eqwd0 4 eqwd0 3 eqwd0 2 eqwd0 1 eqwd0 0 00h r60(3ch) eqaddr eq_addr eqadd 5 eqadd 4 eqadd 3 eqadd 2 eqadd 1 eqadd 0 00h r61(3dh) eqctrl eqram_ctrl eqram _wr eqram _rd 00h r62(3eh) reserved r63(3fh) devadr i2c device address addr7 addr6 addr5 addr4 addr3 addr2 addr1 na(r/w ) e2h r64(40h) portapinwcntrlvrefen vref2 vref1 vref0 00h r65(41h) portainampleftgain aingain l1 aingain l0 00h r66(42h) portainamprightgain aingain r1 aingain r0 00h register name remarks bit[7] bit[6] bi t[5] bit[4] bit[3] bit[2] bit[1] bit[0] defa ult table 20. i2c registers
idt? confidential 52 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo notes : 1 registers not described in this m ap should be considered ?reserved?. 2.29.2.1. spkvol l/r registers speaker (btl) volume adjustment in aux audio mode (port d). this register reset by por/dafg/ulr. writin g to nid22h verb 77f will also cause reset. note: the speaker volume control is intended to be the same volume control as implemented in non aux audio mode but is controlled through the i2c interface rather than the hd audio bus. 2.29.2.2. aic1 register audio interface (i2s) control in aux audio mode r67(43h) dmic0inampleftgain dmic0 ingainl 1 dmic0 ingainl 0 00h r68(44h) dmic0inamprightgain dmic0 ingainr 1 dmic0 ingainr 0 00h r69(45h) adcmuxoutampleftg ain amux mutel amux outgain l5 amux outgain l4 amux outgain l3 amux outgain l2 amux outgain l1 amux outgain l0 90h r70(46h) adcmuxoutampright gain amux muter amux outgain r5 amux outgain r4 amux outgain r3 amux outgain r2 amux outgain r1 amux outgain r0 90h register address bit label type default description 0x01 / 0x02 verb f71/771 (left) verb f72/772 (right) verb 773 (left and right - write only) 7:0 vol[7:0] rw 30 +36 to -91.5db in 0.75db steps 0x00 = +36db 0x01 = +35.25db ... 0x2f = +0.75db 0x30 = 0db 0x31 = -0.75db ... 0xa9 = -90.75 0xaa to 0xfe = -91.5db 0xff = mute register name remarks bit[7] bit[6] bi t[5] bit[4] bit[3] bit[2] bit[1] bit[0] defa ult table 20. i2c registers
idt? confidential 53 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo this register reset by por/dafg/ulr. writin g to nid22h verb 77f will also cause reset. note: the audio interface control is intended to be the sa me as implemented in non aux audio mode but is controlled through the i2c interface rath er than the hd audio bus. 2.29.2.3. aic2 register audio interface (i2s) control in aux audio mode register address bit label type default description 0x06 verb f76/776 7 sclkinv rw 0 0 =sclk not inverted (data and lrclk transition on falling edge of sclk) 1 = invert sclk (data and lrclk transition on rising edge of sclk) 6ms rw1 master/slave 0 = sclk and lrclk are inputs (slave mode) 1 = sclk and lrclk are outputs (master mode) 5lrswap rw0 swap left and right samples 0 = left sample first in frame 1 = right sample first in frame 4lrp rw0 left/right (i2s_lrclk) polarity 0 = default per format 1 = lrclk inverted 3:2 wl[1:0] rw 10 word length 00 = 16 bits 01 = 20 bits 10 = 24 bits 11 = reserved 1:0 format[1:0] rw 10 link format 00 = right justified 01 = left justified 10 = i2s 11 = reserved
idt? confidential 54 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo this register reset by por/dafg/ulr. writin g to nid22h verb 77f will also cause reset. note: the audio interface control is intended to be the sa me as implemented in non aux audio mode but is controlled through the i2c interface rath er than the hd audio bus. 2.29.2.4. aic3 register audio interface (i2s) control in aux audio mode. register address bit label type default description 0x07 verb f77/777 7tri rw0 tri=1 & ms = 0 (slave mode) i2s_dout is hi-z (i2s_sclk and i2s_lrclk are inputs) tri=1 & ms = 1(master mode) i2s_dout, i2s_sclk, and i2s_lrclk are hi-z 6:3 sclk[3:0] rw 0000 sclk rate see table below 2:0 sr[2:0] rw 100 sample rate 000 = 44.1khz 001 = 88.2khz 010= reserved 011 = reserved 100 = 48khz 101 = 96khz 110 = 192khz 111 = reserved sclk[3:0] frequency (mhz) pll clock divisor suggested sample rate clocks/fr ame notes 0000 auto auto all 64 sclk is always 64fs (48khz based rates have jitter) 0001 12.288 147/16 192khz 64 high jitter (<5ns) 0010 6.144 147/32 96khz 64 high jitter (<5ns) 0011 3.072 147/64 48khz 64 high jitter (<5ns) 0100 11.2896 10 88.2khz 128 0101 5.6448 20 88.2khz 64 0110 2.8224 40 44.1khz 64 0111 reserved 1000 auto auto all 64/84 sclk adjusts for sample rate. 44.1khz based rates are 64fs and 48khz based rates are 84fs 1001 16.128 7 192khz 84 1010 8.064 14 96khz 84 1011 4.032 28 48khz 84 1100 7.056 16 88.2khz 80 1101 3.528 32 44.1khz 80 1110 1.764 64 44.1khz 40 1111 reserved
idt? confidential 55 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo this register reset by por/dafg/ulr. writin g to nid22h verb 77f will also cause reset note: the audio interface control is intended to be the sa me as implemented in non aux audio mode but is controlled through the i2c interface rath er than the hd audio bus. 2.29.2.5. pwrm register power management in aux audio mode register address bit label type default description 0x08 verb f78/778 7:6 rsvd ro 00 reserved 5 saen rw 0 1 = input enabled for i2s secondary audio 0 = input disabled for secondary audio 4 auxswap rw 0 swap left and right samples of aux audio output. 0 = left sample first in frame 1 = right sample first in frame 3mclkms rw1 mclk master 0 = mclk is an input 1 = mclk is an output (not recommended in aux audio mode since 24/12mhz rates cant be supported and 112mhz internal clock is imprecise but is useful for testing.) 2:0 mclk[2:0] rw 001 mclk rate 000 = 24mhz (hda bitclk) 001 = 12mhz (hda bitclk/2) 010 = 22.5792mhz 011 = 11.2896mhz 100 = 5.6448mhz 101 = 28.224mhz 110 = 14.112mhz 111 = 7.056mhz
idt? confidential 56 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo this register reset by por/dafg/ulr. writin g to nid22h verb 77f will also cause reset. note: the audio interface control is intended to be the sa me as implemented in non aux audio mode but is controlled through the i2c interface rath er than the hd audio bus. 2.29.2.6. reset register 2.29.2.7. status register this register reset by por/dafg/ulr. writin g to nid22h verb 77f will also cause reset register address bit label type default description 0x09 verb f79/779 7 rsvd ro 0 reserved 6 rsvd ro 0 reserved 5 rsvd ro 0 reserved 4 hppwd rw 0 headphone ports are forced off in aux audio mode (including charge pump) 3 spkron rw 0 btl (port d) is forced on in aux audio mode 2 dmicpwd rw 0 dmic powered down in aux audio mode (including dac) 1mclkout rw1 mclk output enabler 0 = mclk output is disabled in master mode 1 = mclk is an output in master mode (input in slave mode)) 0 auxen rw 1* 1 = aux audio mode enabled (on parts supporting aux audio mode and will override hd audio power state control to enable needed paths.) 0 = aux audio mode disabled (power state controlled by hd audio rules/controls only.) register address bit label type default description 0x0f reset verb f7f/77f 7:0 reset rw 0 writing causes registers to revert to their default values (similar to a function group reset) register address bit label type default description 0x10 status verb f80/780 7 limit1latch ro 0 latched version of limit1, clear via gainctrl_lo[7] 6 limit0latch ro 0 latched version of limit0, clear via gainctrl_lo[7] 5:3 reserved ro 0x0 reserved 2 limit1 ro 0 set (1) if regz saturation afte r gain multiply for ch1. may change on a sample by sample basis. 1 limit0 ro 0 set (1) if regz saturation afte r gain multiply for ch0. may change on a sample by sample basis. 0 zerodet_flag ro 0 set when input zero detect of long string of zeroes.
idt? confidential 57 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 2.29.2.8. init register this register reset by por/dafg/ulr. writin g to nid22h verb 77f will also cause reset 2.29.2.9. config register this register reset by por/dafg/ulr. writin g to nid22h verb 77f will also cause reset 2.29.2.10. pwm4 register this register reset by por/dafg/ulr. writin g to nid22h verb 77f will also cause reset register address bit label type default description 0x11 config1 verb f81/781 7:4 reserved ro 0 reserved 3 anabeep_dcbyp rw 0 1 = bypass analog beep dc filter 2:1 anabeep_dc_coef f rw 0x2 0: dc_coef = 24?h004000; 1: dc_coef = 24?h001000; 2: dc_coef = 24?h000400; 3: dc_coef = 24?h000100; 0 initialize rw 0 1= initialize/soft reset data path. must be set when changing the config0 or config1 registers. register address bit label type default description 0x12 config verb f82/782 7 bpfbyp rw 0 1= bypass monoout band-pass filer 6 prebyp rw 1 1= bypass btl eq filter prescale 5 eqbyp rw 1 1= bypass btl eq filter 4 btl_dcbyp rw 0 1 = bypass btl dc filter 3:1 reserved ro 0 reserved 0 hpfbyp rw 0 1= bypass btl high-pass filter (not dc removal filter) register address bit label type default description 0x13 pwm4 verb f83/783 7 sc_status_clear_right rwc 0 write once o peration will clear sc_fault_status_right 6 sc_status_clear_left rwc 0 write once o peration will clear sc_fault_status_left 5 reserved ro 0 reserved 4 sc_fault_status_right ro 0 1 = fault occurs on right channel 3 sc_fault_status_left ro 0 1 = fault occurs on left channel 2:1 scdly_set rw 00 used for short circuit detection; designer will set the value 0 evenbit rw 0 1=noise shaper output data are even
idt? confidential 58 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 2.29.2.11. pwm3 register this register reset by por/dafg/ulr. writin g to nid22h verb 77f will also cause reset 2.29.2.12. pwm2 register this register reset by por/dafg/ulr. writin g to nid22h verb 77f will also cause reset 2.29.2.13. pwm1registe this register reset by por/dafg/ulr. writin g to nid22h verb 77f will also cause resetr register address bit label type default description 0x14 pwm3 verb f84/784 7:6 outctrl rw 0 pwm output muxing 0 = normal 1 = swap 0/1 2 = ch0 on both 3 = ch1 on both 5:0 cvalue rw 0x2 tristate constant value filed, must be even and not 0 register address bit label type default description 0x15 pwm2 verb f85/785 7:2 dvalue rw 0x10 dvalue constant field. 1 pwm_outflip rw 0 1= swap pwm a/b output pair for all channels 0 pwm_outmode rw 1 1= tristate, 0 = binary register address bit label type default description 0x16 pwm1 verb f86/786 7 reserved ro 0 reserved 6:2 dithpos rw 0 dither position, where dither inserted after ns 0,1,2 = dither bits 2:0 4 = dither bits 3:1 5 = dither bits 4:1 ... 19 = dither bits 19:17 1 dither_range rw 0 1= dither -1 to +1, 0 = dither -3 to +3 0 dithclr rw 0 1 = disable dither
idt? confidential 59 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 2.29.2.14. pwm0 register this register reset by por/dafg/ulr. writin g to nid22h verb 77f will also cause reset register address bit label type default description 0x17 pwm0 verb f87/787 7:6 phaseoffset rw 01 pwm ch1 offset from ch0 at 8x sample rate by: 00 = 0 degrees 01 = 90 degrees 10 = 180 degrees 11 = na 5 clk320mode r 1 1 = pca clock 320 mode 0 = pca clock 294 mode 4 roundup rw 1 1= roundup, 0 = truncate for quantizer 3 bfclr rw 0 1 = disable binomial filter 2 fourthorder rw 0 1 = fourth order binomial filter, 0 = 3rd order binomial filter 1 add3_sel rw 0 1 = 24-bit noise shaper output (pre-quantizer), 0 = 8/9/10-bit quantizer output 0 btl_test_mode rw 0 1 = power stage test mode
idt? confidential 60 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 2.29.2.15. lmtctrl register control operation of the volume limiter (compressor). this register reset by por/dafg/ulr. writin g to nid22h verb 77f will also cause reset 2.29.2.16. lmtatktime (0x19), lmtholdtime (0x1a), lmtreltime (0x1b) registers these 8-bit registers set the timer values between incrementi ng/decrementing the compressor attenuation values. there is one register each for attack, hold, and release times, the configuration parameters are the same for all three and are shown in the table below. these registers reset by por/dafg/ulr. writin g to nid22h verb 77f will also cause reset 2.29.2.17. lmtatkth (0x1d?lo, 0x1c?hi), lmtrelth (0x1f?lo, 0x1e?hi) registers these 16-bit registers set the threshold values. when in attack phase and the attack threshold is exceeded the compressor attenuation is incremented by stepsize (see lm tctrl). when in release phase and the release threshold is not exceeded the compressor attenuation is in cremented by stepsize (but not above 0) these registers reset by por/dafg/ulr. writin g to nid22h verb 77f will also cause reset . register address bit label type default description 0x18 verb f88/788 7:4 ? ro 0 reserved for future use. 3 zerocross rw 0 1 = only change limiter gain value on zero cross. 2:1 stepsize rw 0 gain stepsize when incrementing or decrementing: 0 - 0.75 db, 1 - 1.5 db, 2 - 3.0 db, 3 - 6.0 db 0 limiter_en rw 0 1 = enable limiter (compressor) register address bit label type default description 0x19 lmtatktime verb f89/789 7 atk10ms rw 0 1 = value in bits 6:0 is in 10ms units, otherwise 1ms units. 6:0 lmtat[6:0] rw 0 timer value in units of 1 or 10ms. register address bit label type default description 0x1a lmtholdtime verb f8a/78a 7 hold10ms rw 0 1 = value in bits 6:0 is in 10ms units, otherwise 1ms units. 6:0 lmtht[6:0] rw 0 timer value in units of 1 or 10ms. register address bit label type default description 0x1b lmtatktime verb f8b/78b 7 rel10ms rw 0 1 = value in bits 6:0 is in 10ms units, otherwise 1ms units. 6:0 lmtrt[6:0] rw 0 timer value in units of 1 or 10ms. register address bit label type default description 0x1c lmtatkth_hi verb f8c/78c 7:0 latkth[15:8] rw 7f 8?hff would equal threshold level of +2.0db. each step below this 8-bit full scale value reduces threshold level by 0.0078 db.
idt? confidential 61 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 2.29.2.18. gainctrl_hi register this register reset by por/dafg/ulr. writin g to nid22h verb 77f will also cause reset 2.29.2.19. gainctrl_lo register this register reset by por/dafg/ulr. writin g to nid22h verb 77f will also cause reset register address bit label type default description 0x1d lmtatkth_lo verb f8d/78d 7:0 latkth[7:0] rw ff always 0. it isn?t necessary to provide threshold resolution to the point where these lower 8 bits would be used. register address bit label type default description 0x1e lmtarelth_hi verb f8e/78e 7:0 lrelth[15:8] rw 0 8?hff would equal threshold level of +2.0db. each step below this 8-bit full scale value reduces threshold level by 0.0078 db. register address bit label type default description 0x1f lmtrelth_lo verb f8f/78f 7:0 lrelth[7:0] rw 0 always 0. it isn?t necessary to provide threshold resolution to the point where these lower 8 bits would be used. register address bit label type default description 0x20 gainctrl_hi verb f90/790 7:5 reserved ro 0 reserved 4:3 zerodetlen rw 0x2 enable mute if input consecutive zeros exceeds this length: 00 = 32 01 = 1000 10 = 2000 11 = 4000 2:0 step_time rw 0x5 step time units = 1< idt? confidential 62 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 2.29.2.20. mute register this register reset by por/dafg/ulr. writin g to nid22h verb 77f will also cause reset 2.29.2.21. atten register this register reset by por/dafg/ulr. writin g to nid22h verb 77f will also cause reset 2.29.2.22. dc_coef_sel register this register reset by por/dafg/ulr. writin g to nid22h verb 77f will also cause reset register address bit label type default description 0x22 mute verb f92/792 7:3 reserved ro 0x0 reserved 2 mute rw 0 1 = mute all channels 1 mute1 rw 0 1 = mute ch1 0 mute0 rw 0 1 = mute ch0 register address bit label type default description 0x23 atten verb f93/793 7:0 atten rw 0x0 attenuation. each bit represen ts 0.5db of attenuation to be applied to the channel. the range will be -125db to 2db as follows: 0x00: +2db 0x01: +1.5db 0x02: +1.0db ... 0x47: -33.5db 0x48: -34.0db 0x49: -34.5db ... 0xfe: -125db 0xff: hard master mute register address bit label type default description 0x24 dc_coef_sel verb f94/794 7:3 reserved ro 0 reserved 2:0 dc_coef_sel rw 0x5 0:dc_coef = 24?h100000; //2^^-3 = 0.125 1:dc_coef = 24?h040000; 2:dc_coef = 24?h010000; 3:dc_coef = 24?h004000; 4:dc_coef = 24?h001000; 5:dc_coef = 24?h000400; 6:dc_coef = 24?h000100; //2^^-15 = 0.000330517 7:dc_coef = 24?h000040; //2^^-17
idt? confidential 63 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 2.29.2.23. btl high-pass filter coef_sel register this register reset by por/dafg/ulr. writin g to nid22h verb 77f will also cause reset 2.29.2.24. mono band-pass filter coef_sel register this register reset by por/dafg/ulr. writin g to nid22h verb 77f will also cause reset register address bit label type default description 0x25 hpf_coef_sel verb f95/795 7:3 reserved ro 0 reserved 2:0 hp_coef_sel rw 0x2 select iir coefficients for btl amplifier high pass filter corner frequency 000 = 100hz 001 = 200hz 010 = 300hz 011 = 400hz 100 = 500hz 101 = 750hz 110 = 1000hz 111 = 2000hz register address bit label type default description 0x26 bpf_coef_sel verb f96/796 7 reserved ro 0 reserved 6:4 bph_coef_sel rw 0x3 select iir coefficients for monoout band-pass filter lower corner frequency 000 = 63hz 001 = 80hz 010 = 100hz 011 = 120hz 100 = 150hz 101 = 200hz 110 = 315hz 111 = 400hz 3 reserved ro 0 reserved 2:0 bpl_coef_sel rw 0x2 select iir coefficients for monoout band-pass filter upper corner frequency 000 = 150hz 001 = 200hz 010 = 250hz 011 = 315hz 100 = 400hz 101 = 500hz 110 = 630hz 111 = 800hz
idt? confidential 64 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 2.29.2.25. porta pinwcntrlvrefen register this register reset by por/dafg/ulr. writin g to nid22h verb 77f will also cause reset 2.29.2.26. porta inampleftgain register this register reset by por/dafg/ulr. writin g to nid22h verb 77f will also cause reset 2.29.2.27. porta inamprightgain register this register reset by por/dafg/ulr. writin g to nid22h verb 77f will also cause reset 2.29.2.28. dmic0 inampleftgain register this register reset by por/dafg/ulr. writin g to nid22h verb 77f will also cause reset register address bit label type default description 0x40 porta_vrefen 7:3 rsvd ro 00000 reserved 2:0 vref rw 000 vref selection for port a. see vrefcntrl field of pincap parameter for supported selections 000 = hi-z 001 = 50% 010 = gnd 011 = reserved 100 = 80% 101 = 100% 110 = reserved 111 = reserved register address bit label type default description 0x41 porta_gainl 7:2 rsvd ro 000000 reserved 1:0 aingainl rw 00 input gain step number for po rt a. see inam pcap parameter pertaining to this widget register address bit label type default description 0x42 porta_gainr 7:2 rsvd ro 000000 reserved 1:0 aingainr rw 00 input gain step number for port a. see inampcap parameter pertaining to this widget register address bit label type default description 0x43 dmic0_gainl 7:2 rsvd ro 000000 reserved 1:0 dmic0ingainl rw 00 input gain step number for dm ic0. see inampcap parameter pertaining to this widget
idt? confidential 65 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 2.29.2.29. dmic0 inamprightgain register this register reset by por/dafg/ulr. writin g to nid22h verb 77f will also cause reset 2.29.2.30. adc0mux outampleftgain register this register reset by por/dafg/ulr. writin g to nid22h verb 77f will also cause reset 2.29.2.31. adc0mux outamprightgain register this register reset by por/dafg/ulr. writin g to nid22h verb 77f will also cause reset register address bit label type default description 0x44 dmic0_gainr 7:2 rsvd ro 000000 reserved 1:0 dmic0ingainr rw 00 input gain step number for dmic0. see inampcap parameter pertaining to this widget register address bit label type default description 0x45 adc0mux_gainl 7 amuxmutel rw 1 amp mute: 1=muted, 0=not muted 6 rsvd ro 0 reserved 5:0 amuxoutgainl rw 010000 output gain step number for adc0mux. see outampcap parameter pertaining to this widget register address bit label type default description 0x46 adc0mux_gainr 7 amuxmuter rw 1 amp mute: 1=muted, 0=not muted 6 rsvd ro 0 reserved 5:0 amuxoutgainr rw 010000 output gain step number fo r adc0mux. see outampcap parameter pertaining to this widget
idt? confidential 66 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 2.29.2.32. btl class-d power stage register settings this register reset by por/dafg/ulr. register address bit label type default description 0x27 test and control left verb f97/797 7 enable rw 1 1 = enable btl power stage 6 trc_esd ro 0 1 = esd trigger detected 0 = no trigger 5 strendrv rw 0 1 = strengthen pre-drive 0 = normal 4:3 scthr rw 01 short circuit th reshold current 00 = 10% of pvdd 01 = 14% of pvdd 10 = 16% of pvdd 11 = 20% of pvdd 2:0 deadtime rw 001 dead time for output fets 000 = 0.5ns 001 = 1.0ns 010 = 1.5ns 011 = 2ns 100 = 4ns 101 = 8ns 110 = 8ns 111 = 8ns register address bit label type default description 0x28 short circuit left verb f98/798 7 test_en rw 0 1 = enable short circuit test 6 sc_dis rw 0 1 = disable short circuit protection 5 rsvd rw 0 reserved 4 fault_sc ro 0 1 = fault 3 rsvd rw 0 reserved 2 pnsel rw 0 1=pfet tested, 0=nfet tested 1 force_sc rw 0 1 = force short circuit 0 test rw 0 1 = pos pfet / neg nfet on, 0 = pos nfet / neg pfet on
idt? confidential 67 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 2.29.2.33. ldo level control register this register reset by por/dafg/ulr register address bit label type default description 0x29 test and control right verb f99/799 7 enable rw 1 1 = enable btl power stage 6 trc_esd ro 0 1 = esd trigger detected 0 = no trigger 5 strendrv rw 0 1 = strengthen pre-drive 0 = normal 4:3 scthr rw 01 short circuit threshold current 00 = 10% of pvdd 01 = 14% of pvdd 10 = 16% of pvdd 11 = 20% of pvdd 2:0 deadtime rw 001 dead time for output fets 000 = 0.5ns 001 = 1.0ns 010 = 1.5ns 011 = 2ns 100 = 4ns 101 = 8ns 110 = 8ns 111 = 8ns register address bit label type default description 0x2a short circuit right verb f9a/79a 7 test_en rw 0 1 = enable short circuit test 6 sc_dis rw 0 1 = disable short circuit protection 5 rsvd rw 0 reserved 4 fault_sc ro 0 1 = fault 3 rsvd rw 0 reserved 2 pnsel rw 0 1=pfet tested, 0=nfet tested 1 force_sc rw 0 1 = force short circuit 0 test rw 0 1 = pos pfet / neg nfet on, 0 = pos nfet / neg pfet on register address bit label type default description 0x2b ldo level control verb f9b/79b 7:3 reserved ro 0x0 reserved 2 lv_quad_bias rw 0 1:0 lv_reg_cntrl_bit rw 0x0 two bits are defined to program the output of the 1.8v ldo 00 = normal operation (3.3v in to 1.8v out) 01 = 1.8v*1.1 = 1.98v 10 = 1.8v*0.9 = 1.62v11 = power down ldo/bypass. when disabled, the dvdd_core pin must be supplied with a nominal 1.8v from an external source.
idt? confidential 68 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 2.29.2.34. eqram the eq ram is a 52 x 48-bit sram that contains the eq coefficients. this register reset by por/dafg/ulr or when a bi st is run under certain conditions, contact idt for more informat ion. writing to nid22h verb 77 f will cause not generate a reset. . address channel right coefficients (24b it) channel left coefficients (24bit) eqram bits [47:24] [23:00] based on 44.1khz sample rate 0x00 eq_coef_f0_b0 eq_coef_f0_b0 0x01 eq_coef_f0_b1 eq_coef_f0_b1 0x02 eq_coef_f0_b2 eq_coef_f0_b2 0x03 eq_coef_f0_a1 eq_coef_f0_a1 0x04 eq_coef_f0_a2 eq_coef_f0_a2 0x05 eq_coef_f1_b0 eq_coef_f1_b0 0x06 eq_coef_f1_b1 eq_coef_f1_b1 0x07 eq_coef_f1_b2 eq_coef_f1_b2 0x08 eq_coef_f1_a1 eq_coef_f1_a1 0x09 eq_coef_f1_a2 eq_coef_f1_a2 0x0a eq_coef_f2_b0 eq_coef_f2_b0 0x0b eq_coef_f2_b1 eq_coef_f2_b1 0x0c eq_coef_f2_b2 eq_coef_f2_b2 0x0d eq_coef_f2_a1 eq_coef_f2_a1 0x0e eq_coef_f2_a2 eq_coef_f2_a2 0x0f eq_coef_f3_b0 eq_coef_f3_b0 0x10 eq_coef_f3_b1 eq_coef_f3_b1 0x11 eq_coef_f3_b2 eq_coef_f3_b2 0x12 eq_coef_f3_a1 eq_coef_f3_a1 0x13 eq_coef_f3_a2 eq_coef_f3_a2 0x14 eq_coef_f4_b0 eq_coef_f4_b0 0x15 eq_coef_f4_b1 eq_coef_f4_b1 0x16 eq_coef_f4_b2 eq_coef_f4_b2 0x17 eq_coef_f4_a1 eq_coef_f4_a1 0x18 eq_coef_f4_a2 eq_coef_f4_a2 0x19 eq_prescale eq_prescale based on 48khz sample rate 0x1a eq_coef_f0_b0 eq_coef_f0_b0 0x1b eq_coef_f0_b1 eq_coef_f0_b1 0x1c eq_coef_f0_b2 eq_coef_f0_b2 0x1d eq_coef_f0_a1 eq_coef_f0_a1 0x1e eq_coef_f0_a2 eq_coef_f0_a2 0x1f eq_coef_f1_b0 eq_coef_f1_b0 0x20 eq_coef_f1_b1 eq_coef_f1_b1 0x21 eq_coef_f1_b2 eq_coef_f1_b2 0x22 eq_coef_f1_a1 eq_coef_f1_a1
idt? confidential 69 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo the eqram is programmed indirectly through the control bus in the following manner: 1) write the 48-bit write data to the eqram_write register 2) write the target addre ss to the eq_address register 3) set bit 7 of the eqram_ctrl register the write will occur when the eqram is not being access ed by the dsp audio proce ssing routines. when complete the hardware will automa tically clear this bit. reading back from the eqram is done in the following manner: 1) write target address to eq_addr register 2) set bit 6 of the eqram_ctrl register when the hardware comple tes the read it will automa tically clear this bit. 3) when bit 6 of the eqram_ctrl register has been cleare d, read the 48bit data from the eqram_read register. 2.29.2.35. eqram read data (0x30?0x35), eqram write data (0x36?3b) registers these two 48-bit registers (addressed as 12 8-bit registers) are 48-bit data holding registers used when doing indirect writes/reads to the eqram. these registers reset by por/dafg/ulr ]the eqram_write will also reset by writing to nid22h verb 77f ] 0x23 eq_coef_f1_a2 eq_coef_f1_a2 0x24 eq_coef_f2_b0 eq_coef_f2_b0 0x25 eq_coef_f2_b1 eq_coef_f2_b1 0x26 eq_coef_f2_b2 eq_coef_f2_b2 0x27 eq_coef_f2_a1 eq_coef_f2_a1 0x28 eq_coef_f2_a2 eq_coef_f2_a2 0x29 eq_coef_f3_b0 eq_coef_f3_b0 0x2a eq_coef_f3_b1 eq_coef_f3_b1 0x2b eq_coef_f3_b2 eq_coef_f3_b2 0x2c eq_coef_f3_a1 eq_coef_f3_a1 0x2d eq_coef_f3_a2 eq_coef_f3_a2 0x2e eq_coef_f4_b0 eq_coef_f4_b0 0x2f eq_coef_f4_b1 eq_coef_f4_b1 0x30 eq_coef_f4_b2 eq_coef_f4_b2 0x31 eq_coef_f4_a1 eq_coef_f4_a1 0x32 eq_coef_f4_a2 eq_coef_f4_a2 0x33 eq_prescale eq_prescale register address bit label type default description 30h eqram_read[47:40] verb fa0/7a0 7:0 eqrd[47:40] rw 0x00 48-bit data register, contains the contents of the most recent eqram address read from the ram. the address read will have been specified by the eqram address fields. address channel right coefficients (24b it) channel left coefficients (24bit) eqram bits [47:24] [23:00]
idt? confidential 70 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo register address bit label type default description 31h eqram_read[39:32] verb fa1/7a1 7:0 eqrd[39:32] rw 0x00 48-bit data register, contains the contents of the most recent eqram address read from the ram. the address read will have been specified by the eqram address fields. register address bit label type default description 32h eqram_read[31:24] verb fa2/7a2 7:0 eqrd[31:24] rw 0x00 48-bit data register, contains the contents of the most recent eqram address read from the ram. the address read will have been specified by the eqram address fields. register address bit label type default description 33h eqram_read[23:16] verb fa3/7a3 7:0 eqrd[23:16] rw 0x00 48-bit data register, contains the contents of the most recent eqram address read from the ram. the address read will have been specified by the eqram address fields. register address bit label type default description 34h eqram_read[15:8] verb fa4/7a4 7:0 eqrd[15:8] rw 0x00 48-bit data register, contains t he contents of the most recent eqram address read from the ram. the address read will have been specified by the eqram address fields. register address bit label type default description 35h eqram_read[7:0] verb fa5/7a5 7:0 eqrd[7:0] rw 0x00 48-bit data register, contains th e contents of the most recent eqram address read from the ram. the address read will have been specified by the eqram address fields. register address bit label type default description 36h eqram_write[47:40] verb fa6/7a6 7:0 eqwd[47:40] rw 0x00 48-bit data register, contains th e values to be written to the eqram. the address written will have be specified by the eqram address fields. register address bit label type default description 37h eqram_write[39:32] verb fa7/7a7 7:0 eqwd[39:32] rw 0x00 48-bit data register, contains the values to be written to the eqram. the address written w ill have be specified by the eqram address fields. register address bit label type default description 38h eqram_write[31:24] verb fa8/7a8 7:0 eqwd[31:24] rw 0x00 48-bit data register, contains th e values to be written to the eqram. the address written will have be specified by the eqram address fields. register address bit label type default description 39h eqram_write[23:16] verb fa9/7a9 7:0 eqwd[23:16] rw 0x00 48-bit data register, contains the values to be written to the eqram. the address written w ill have be specified by the eqram address fields.
idt? confidential 71 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 2.29.2.36. eqram address register this 8-bit register provides the add ress to the internal ram when doing indirect writes/reads to the eqram this register reset by por/dafg/ulr. writin g to nid22h verb 77f will also cause reset. 2.29.2.37. eqram control register this control register provides the write/read enabl e when doing indirect writes/reads to the eqram. this register reset by por/dafg/ulr. writin g to nid22h verb 77f will also cause reset.i 2.29.2.38. device address register this 8-bit register provides slave addre ss for the device on the control interface. register address bit label type default description 3ah eqram_write[15:8] verb faa/7aa 7:0 eqwd[15:8] rw 0x00 48-bit data register, contains the values to be written to the eqram. the address written will have be specified by the eqram address fields. register address bit label type default description 3bh eqram_write[7:0] verb fab/7ab 7:0 eqwd[7:0] rw 0x00 48-bit data register, contains th e values to be written to the eqram. the address written will have be specified by the eqram address fields. register address bit label type default description 3ch eqram_addr verb fac/7ac 7:6 rsvd ro 0x00 reserved 5:0 eqadd[5:0] rw 0x00 contains the address (between 0x00 and 0x33) of the eqram to be accessed by a read or write. this is not a byte address--it is the address of the 48-bit data item to be accessed from the eqram. register address bit label type default description 3dh eqram_control verb fad/7ad 7 eqram_wr rw 0 1 = write to eqram, cleared by hw when done 6 eqram_rd rw 0 1 = read from eqram, cleared by hw when done 5:0 rsvd ro 0 reserved register address bit label type default description 3fh dev_adr verb faf/7af 7:1 devadr[7:1] rw 1110 001 contains the 7-bit device address used when accessing the codec in aux audio mode. the lsb is ignored and reads back 0. (d0 is the read/write bit) 0 devadr[0] ro 0 this bit is not used.
idt confidential 72 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 3. characteristics 3.1. electrical specifications 3.1.1. absolute maximum ratings stresses above the ratings lis ted below can cause permanent dam age to the 92HD92. these rat- ings, which are standard values for idt commercially rated parts, are stress ratings only. functional operation of the device at these or any other condi tions above those indicated in the operational sec- tions of the specifications is not implied. expo sure to absolute maximu m rating conditions for extended periods can affect pro duct reliability. electrical parame ters are gua ranteed only over the recommended operating temperature range. 3.1.2. recommended operating conditions item pin maximum rating analog maximum supply voltage avdd 6 volts digital maximum supply voltage dvdd 5.5 volts pvdd 6 volts vrefout output current 5 ma voltage on any pin relative to ground vss - 0.3 v to vdd + 0.3 v operating temperature 0 o c to +70 o c storage temperature -55 o c to +125 o c soldering temperature soldering temperature information for all available in the package section of this datasheet. table 21. electrical specifi cation: maximum ratings parameter min. typ. max. units power supplies dvdd_core 1.6 1.8 1.98 v dvdd_io (3.3v signaling) 3.135 3.3 3.465 v dvdd_io (1.5v signaling) 1.418 1.5 1.583 v power supply voltage digital - 3.3 v 3.135 3.3 3.465 v analog - 5 v 4.75 5 5.25 v ambient operating temperature 0 +70 ? c case temperature t case (48-qfn) +90 ? c table 22. recommended operating conditions esd: the 92HD92 is an esd (electrostatic discharge) sens itive device. the human body and test equipment can accumulate and discharge electrostatic charges up to 4000 vo lts without detection. even though the 92HD92 implements internal esd protection circuitry, proper esd precautions sh ould be followed to avoid damaging the functionality or performance.
idt confidential 73 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 3.2. 92HD92 analog perfor mance characteristics (preliminary) (t ambient = 25 oc, avdd = 4.75v (4.5-5.25v) or 3.3v +/-5%, dvdd = 3.3v 5% or 1.8v 10%, avss=dvss=0v; 20hz to 20khz swept sinusoidal input; sample frequency = 48 khz; 0db fs = 1vrms for avdd = 4.75v and 0.71vrms for avdd = 3.3v, 10k ? //50pf load, testbench characterization bw: 20 hz ? 20 khz, 0 db settings on all gain stages) parameter conditions min typ max unit digital to analog converters resolution 24 bits dynamic range 1 : pcm to all analog outputs -60db fs signal level, analog mixer disabled 98 db snr 2 - dac to all line-out ports analog mixer disabled, pcm data 98 db thd+n 3 - dac to all line-out ports analog mixer disabled,-3db fs signal, pcm data 89 dbr snr 2 - dac to all headphone ports analog mixer disabled, 10k ? load, pcm data 98 db thd+n 3 - dac to all headphone ports analog mixer disabled,-3db fs signal, 10k ? load, pcm data 87 dbr snr 2 - dac to all headphone ports analog mixer disabled, 32 ? load, pcm data 98 db thd+n 3 - dac to all headphone ports analog mixer disabled, -3db fs signal, 32 ? load, pcm data 73 dbr any analog input (adc) to dac crosstalk 10khz signal frequency. 0dbv signal applied to adc, dacs idle, ports enabled as output. -65 - - db any analog input (adc) to dac crosstalk 1khz signal frequency. see above -65 - - db dac l/r crosstalk dac to lo or hp 20-15khz into 10k ? load 70 73 db dac l/r crosstalk dac to hp 20-15khz into 32 ? load 65 68 db gain error analog mixer disabled 0.5 db interchannel gain mismatch analog mixer disabled 0.5 db d/a digital filter pass band 4 20 - 21,000 hz d/a digital filter pass band ripple 5 0.125 +/- db d/a digital filter transition band 21,000 - 31,000 hz d/a digital filter stop band 31,000 - - hz d/a digital filter stop band rejection 6 -100 - - db d/a out-of-band rejection 7 -55 - - db group delay (48khz sample rate) - - 1 ms attenuation, gain step size digital - 0.75 - db dac offset voltage - 10 20 mv deviation from linear phase - 1 10 deg. analog outputs full scale all mono/line-outs dac pcm data 1.00 - - vrms full scale all mono/line-outs dac pcm data 2.83 - - vp-p table 23. 92HD92 analog pe rformance characteristics
idt confidential 74 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo all headphone capable outputs 32 ?? load 40 60 - mw (peak) amplifier output impedance mono/line outputs headphone outputs 150 0.1 ohms external load capacitance mono/line outputs headphone outputs 220 pf analog inputs full scale input voltage 0db boost @4.75v (input voltage required for 0db fs output) 1.05 - - vrms all analog inputs with boost 10db boost 0.320 - - vrms all analog inputs with boost 20db boost 0.105 - - vrms all analog inputs with boost 30db boost 0.032 - - vrms boost gain accuracy -2 2 db input impedance - 50 - k ? input capacitance - 15 - pf analog mixer dynamic range: pcm to all analog outputs -60db fs signal level analog beep enabled all other mixer inputs mute 95 db snr 2 - all line-inputs to all line outputs all inputs unmuted, single line input driven by ate. 90 db thd+n 3 - all line-inputs to all line outputs 0db full scale input on one input, all others silent. 83 dbr snr 2 - dac to all ports analog mixer enabled, pcm data, all others inputs mute. 98 db thd+n 3 - dac to all ports analog mixer enabled, 0db fs signal, pcm data, all others inputs unmute/silent 85 dbr attenuation, gain step size analog - 1.5 - db analog to digital converter resolution 24 bits full scale input voltage 0db boost (input voltage required to generate 0dbfs per aes 17) 1.05 dynamic range 1 , all analog inputs to a/d high pass filer enabled, -60db fs, no boost 94 db full scale input voltage 20db boost (input voltage required to generate 0dbfs per aes 17) 0.105 dynamic range 1 , all analog inputs to a/d 20db boost high pass filter enabled, -60db fs 90 db thd+n 3 all analog inputs to a/d high pass filter enabled, -3db fs signal level 83 db thd+n 3 all analog inputs to a/d 20db boost, high pass filter enabled, -3db fs signal level 80 db analog frequency response 8 10 - 30,000 hz a/d digital filter pass band 4 20 - 21,000 hz a/d digital filter pass band ripple 5 0.1 +/- db parameter conditions min typ max unit table 23. 92HD92 analog pe rformance characteristics
idt confidential 75 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo a/d digital filter transition band 21,000 - 31,000 hz a/d digital filter stop band 31,000 - - hz a/d digital filter stop band rejection 6 -100 - - db group delay 48 khz sample rate - - 1 ms any unselected analog input to adc crosstalk 10khz signal frequency -65 - - db any unselected analog input to adc crosstalk 1khz signal frequency -65 - - db adc l/r crosstalk any selected input to adc 20-15khz -65 db dac to adc crosstalk dac output 0dbfs. all outputs loaded. input to adc open. 20-15khz -65 db spurious tone rejection 9 - -100 - db attenuation, gain step size (analog) - 1.5 - db interchannel gain mismatch adc - - 0.5 db power supply power supply rejection ratio 10khz - -60 - db power supply rejection ratio 1khz - -70 - db d0 didd 10 3.3v 25 ma d0 aidd 10 5v 66 ma d0 didd 11 3.3v 17 ma d0 aidd 11 5v 54 ma d1 didd 12 3.3v 10 ma d1 aidd 12 5v 30 ma d2 didd 3.3v 8 ma d2 aidd 5v 7 ma d3 (beep enabled) didd 13 3.3v 2 ma d3 (beep enabled) aidd 13 5v 6 ma d3 didd 13 3.3v 2 ma d3 aidd 13 5v 4 ma d3cold didd 13 3.3v 1.3 ma d3cold aidd 13 5v 3.5 ma vendor d4 didd 3.3v 1.1 ma vendor d4 aidd 5v 3.5 ma vendor d5 didd 3.3v 1 ma vendor d5 aidd 5v 0.3 ma voltage reference outputs vrefout 14 - 0.5 x avdd - v vrefout drive 1.6 ma parameter conditions min typ max unit table 23. 92HD92 analog pe rformance characteristics
idt confidential 76 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 3.3. class-d btl ampl ifier performance table 24. class-d btl amplifier performance vrefilt (vag) 0.45 x avdd v phased locked loop pll lock time 96 200 usec pll (or hd audio bit clk) 24mhz clock jitter 150 500 psec esd / latchup iec1000-4-2 1 level jesd22-a114-b 2 class jesd22-c101 4 class 1.dynamic range is the ratio of the full scale signal to the noise output with a -60dbfs signal as defined in aes17 as snr in the presence of signal and outlined in aes6id, measured ?a weig hted? over 20 hz to 20 khz bandwidth 2.ratio of full scale signal to idle channel noise output is measured ?a weighted? over a 20 hz to a 20 khz bandwidth. (aes17-1991 idle channel noise or eiaj cp-307 signal-to-noise ratio). 3.thd+n ratio as defined in aes17 and outlined in aes6id ,non-weighted, over 20 hz to 20 khz bandwidth .results at the jack are dependent on external components and will likely be 1 - 2db worse. 4.peak-to-peak ripple over passband meets 0.125db limits, 48 khz or 44.1 khz sample frequency. 1db limit. 5. peak-to-peak ripple over passband m eets 0.125db limits, 48 khz or 44.1 khz sample frequency. 1db limit. 6.stop band rejection determines f ilter requirements. out-of-band re jection determines audible noise. 7.the integrated out-of-band nois e generated by the dac process, during normal pcm audio playback, over a bandwidth 28.8 to 100 khz, with respect to a 1 vrms dac output. 8. 1db limits for line output & 0 db gain, at -20dbv 9.spurious tone rejection is test ed with adc dither enabled and compared to adc performance without dither. 10.all functions/converters active, pin comp lexes enabled, two fdx streams, line (10k ohm) loads. add 24ma analog current per stereo 32 ohm headphone. 11.one stereo dac and corresponding pin widgets enabled (playback mode) 12.mixer enabled 13.idle measurement d3 set for minimum clicks/pops (biases and min. amps. on) 14.can be set to 0.5 or 0.8 avdd. parameter min typ max unit output power (btl 4 ohm, 5v) 2 w amplifier efficiency ?? (4 ? , 5v, 2w) 88 % thd+n (btl 4 ? , 5v, fs) 1% thd+n (btl 4 ? , 5v, -3dbfs) 0.3 % frequency response 20 - 20k hz pwm frequency 352.8 khz output voltage noise (4 ? , 5v) 65 uv idle current 3.6 ma shutdown current 0 ma parameter conditions min typ max unit table 23. 92HD92 analog pe rformance characteristics
idt confidential 77 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 3.4. capless headphone supply characteristics 3.5. ac timing specs 3.5.1. hd audio bus timing figure 21. hd audio bus timing parameter min typ max unit ldo idle current 1 2 ma capless headphone amp idle current 2 3 ma charge pump idle current 4 6 ma charge pump shutdown time 1 ms charge pump start-up time 10 ms frequency 384 khz c1/c2 cap value 2.2 uf table 25. capless headphone supply parameter definition symbol min typ max units bclk frequency average bclk frequency 23.9976 24.0 24.0024 mhz bclk period period of bclk including jitter tcyc 41.163 41.67 42.171 ns bclk high phase high phase of bclk t_high 17.5 24.16 ns bclk low phase low phase of bclk t_low 17.5 24.16 ns bclk jitter bclk jitter 150 500 ps sdi delay time after rising edge of bclk that sdi becomes valid t_tco 3 11 ns sdo setup setup for sdo at both rising and falling edges of bclk t_su 5 ns sdo hold hold for sdo at both rising and falling edges of bclk t_h 5 ns table 26. hd audio bus timing
idt confidential 78 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 3.5.2. spdif timing 3.5.3. digital microphone timing 3.5.4. gpio characteristics parameter definition symbol min typ max units spdif_out frequency highest rate of encoded signal 64 times the sample rate 2.8224 3.072 12.288 mhz spdif_out unit interval 1/(128 times the sample rate) ui 177.15 162.76 40.69 ns spdif_out jitter spdif_out jitter 4.43 ns spdif_out rise time t_rise 15 ns spdif_out fall time t_fall 15 ns table 27. spdif timing parameter definition symbol min typ max units dmic_clk frequency average dmic_c lk frequency 1.176 2.352 4.704 mhz dmic_clk period period of dmic_c lk tdmic_cyc 850.34 425.17 212.59 ns dmic_clk jitter dmic_clk jitter 5000 ps dmic data setup setup for the microphone data at both rising and falling edges of dmic_clk tdmic_su 5 ns dmic data hold hold for the microphone data at both rising and falling edges of dmic_clk tdmic_h 5 ns table 28. digital mic timing parameter definition symbol min typ max units input high voltage 1 1.high peak currents during dynamic switching of the class-d pwm outputs can result in gr ound rail bounce. the amount of ground bounce should be kept below 0.35 x vdd for all in puts, including internal logic which is tied to dvdd_core. input level at or above which a 1 is reliably recorded vih 0.6 x vdd v input low voltage 1 input level at or below which a 0 is reliably recorded. vdd may be dvdd or avdd vil 0.35 x vdd v output high voltage iout = 4ma vdd may be dvdd or avdd depending on pin voh 0.9 x vdd v output low voltage iout = -4ma vdd may be dvdd or avdd depending on pin vol 0.1 x vdd v input rise/fall time transition time between 10% and 90% of supply t_rise/t_fall 10 ns input/tristate high leakage current vin = vdd vdd may be dvdd or avdd depending on pin (does not include pull-up or pull-down resistor if present) 0.5 ua input/tristate low leakage current vin = 0 vdd may be dvdd or avdd depending on pin (does not include pull-up or pull-down resistor if present) -50 ua table 29. gpio characteristics
idt confidential 79 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 3.5.5. i2s interface timing parameter definition symbol min typ max units i2s_mclk frequency mclk frequency (256fs) 12.288 mhz i2s_sclk frequency sclk frequency (64fs) 3.072 mhz i2s_sclk jitter dmic_clk jitter 4000 ps i2s data setup setup for input and output data relative to i2s_sclk ti2s_su 5 ns i2s data hold hold for input and output data relative to i2s_sclk ti2s_h 5 ns table 30. i2s interface timing
idt confidential 80 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 4. functional block diagram figure 22. functional block diagram stream & channel select dac 0 stream & channel select stream & channel select hd audio link logic pcm to spdif out spdif out0 / aux_out (shared) volume & mute dac 1 digital mute mux adc0 pin 48 pin 4 dmic_0 dmic_0 mux adc1 mux dmic_1 (shared) dmic_1 pin 46 stream & channel select vol mute analog pc_beep digital microphone volume and mute is done after the adc but shown here and in widget list as same as analog path. stream & channel select pcm to spdif out adc0 mux adc1 dac0 dac1 boost +0/+10/+20/+30 db boost +0/+10/+20/+30 db dmic dmic pin 46 pin complex pins 40/41/43/44 port d port e adc0 stream & channel select vol gain mute -16 to +30 db in 1 db steps spdif out1 / dmic1 / aux_in (shared) adc1 vol gain mute -16 to +30 db in 1 db steps i2s 0,-6,-12,-18db port f i2s mono lo pin complex pin 25 pin complex pins 17/18 pin complex pins 15/16 vol pin complex pins 28/29 port a boost +0/+10/+20/+30 db port a hp pin complex pins 31/32 port b hp cap-less mux ? analog beep digital pc beep mux ? analog beep digital pc beep mux ? analog beep digital pc beep mic bias dac1 mixeroutvol dac0 mux dac1 mixeroutvol dac0 mux dac1_dig mixeroutvol_dig dac0_dig mux btl class-d digital pwm controller mux ? analog beep_dig digital pc beep dac1_dig dac0_dig mux src dac 2 dac0_dig dac1_dig mixeroutvol_dig highpass filter 5- band eq clocking boost +0/+10/+20/+30 db port f vol mute 0,-6,-12,-18db detect/convert analog beep analog beep_dig beep_active ? vol mute vol mute mixer -34.5 to +12 db in 1.5 db steps port a vol mute dac0 dac1 vol -46.5 to 0 db in 1.5 db steps mute mixeroutvol adc mixeroutvol_dig bandpass filter dac m ? stereo to mono mix mux ? analog beep_dig digital pc beep dac1_dig dac0_dig mux mixeroutvol_dig mixer port f dmic0 dmic1 port a mux mixer port f dmic0 dmic1 port a mux vol mute port f digital mix secondary audio i2s i2s i2s aux_out pin 48 (shared) aux_in pin 46 (shared) i2s_secondary pin 12 ? port f routing port d port e port a port b dmic0
idt confidential 81 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 5. widget diagram figure 23. widget diagram vendor specific test hda link spdif out1 nid = 1eh nid = 20h dig1pin adc0 mux adc1 mux dac0 digital adc0 nid = 15h dmic0 nid = 11h port b port a nid = 0ah analog* analog* dac0 nid = 13h volume mute lo mixer nid = 17h adc0 mux volume mute dmic0 mixer dmic1 nid = 18h vol dmic1 vol (vsw) nid = 12h digital vol adc1 nid = 16h dac1 mixeroutvol nid = 0bh vsw nid = 0ch port d nid = 0dh port e nid = 0eh port f nid = 0fh dac1 nid = 14h volume mute 10/20/30 10/20/30 -16 to 30db 1db step -95.25 to 0db 0.75db step -95.25 to 0db 0.75db step spdif out0 nid = 1dh nid = 1fh dig0pin adc1 mux digital adc0 mux pc_beep nid = 21h digital adc1 mux adc0 mux hp btl pc_beep (pin 12) mute volume nid = 1bh ? -34.5 to +12db in 1.5db steps dac0 dac1 in vol 10/20/30 in vol 10/20/30 hp port f adc1 mux volume mute -16 to 30db 1db step port f 0,-6,-12,-18db vsv mono nid = 10h lo dac0 dac1 mixeroutvol dac0 dac1 mixeroutvol dac0 dac1 mixeroutvol dmic0 dmic1 vendor specific test d d ? nodes are digital capable d d d port a port a vsw nid = 22h mute volume mute volume port f mute volume mute volume to all ports enabled as an output to all ports enabled as an output nid = 1ch mixeroutvol volume -46.5 to 0db in 1.5db steps mixer mixeroutvol mute bias in vol 10/20/30 nid = 1ah nid = 19h mono mix mono mux dac0 dac1 mixeroutvol dmic0 mixer dmic1 port f port a port a dac0 dac1 eq aux_in digital i2s_secondary (pin 12) digital nid = 1bh secondary audio digital aux_out
idt confidential 82 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 6. port and pin configurations 6.1. port configurations figure 24. port configurations a m p d internal spdif_out *eapd hdmi/display port a m p m external b hp side a mic/hp f mic (using i2s) hp (using i2s) e dock mobile digital mic array
idt confidential 83 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 6.2. pin configuration defa ult register settings the following table shows the pin widget configuration defa ult settings. desktop implementation with 2 jacks in front and 3 jacks in rear. the internal speaker is redirected from the front (green) h eadphone jack. an in ternal microphone is present. figure 25. pin name port location device connection color misc assoc. seq portapin connect to jack 00b mainboard front 2h mic in ah 1/8 inch jack 1h pink 9h jack detect override=0 2h 0h portbpin connect to jack 00b mainboard front 2h hp out 2h 1/8 inch jack 1h green 4h jack detect override=0 1h fh portcpin na portdpin internal 10b na 010000b speaker 1h other analog 7h unknown 0h jack detect override=1 1h 0h portepin connect to jack 00b mainboard rear 1h hp out 2h 1/8 inch jack 1h green 4h jack detect override=0 5h 0h portfpin connect to jack 00b mainboard rear 1h line in 8h 1/8 inch jack 1h blue 3h jack detect override=0 2h eh monooutpin no connect 01b na 000000b other fh unknown 0h unknown 0h jack detect override=0 fh 0h digoutpin0 connect to jack 00b mainboard rear 000001b spdif out 4h optical 5h black 1h jack detect override=1 6h 0h digoutpin1 connect to jack 10b internal 011000b digital other out 5h other digital 6h unknown 0h jack detect override=1 7h 0h digmic0pin internal 10b internal 010000b mic in ah atapi 3h unknown 0h jack detect override=1 3h 0h table 31. pin configuration default settings
idt confidential 84 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7. widget information there are two types of responses: solicited and un solicited. solicited responses are provided as a direct response to an issued command and will be provided in the frame immediately following the command. unsolicited responses are provided by the codec independent of any command. unso- licited responses are the result of codec events su ch as a jack insertion detection. the formats for solicited responses and un solicited responses are shown in the tables below. the ?tag? field in bits [31:28] of the unsolicited response identify the event. bits [39:32] bits [31:28] bits [27:20] bits[19:16] bits [15:0] reserved codec address nid verb id (4-bit) payload data (16-bit) table 32. command format for verb with 4-bit identifier bits [39:32] bits [31:28] bits [27:20] bits[19:8] bits [7:0] reserved codec address nid verb id (12-bit) payload data (8-bit) table 33. command format for verb with 12-bit identifier bit [35] bit [34] bits [33:32] bits[31:0] valid (valid = 1) unsol = 0 reserved response table 34. solicited response format bit [35] bit [34] bits [33:32] bits[31:28] bits [27:0] valid (valid = 1) unsol = 1 reserved tag response table 35. unsolicited response format
idt confidential 85 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.1. widget list table 36. widget list id widget name description 00h root root node 01h afg audio function group 0ah port a port a pin widget (headphone, line in/out, mic) 0bh port b port b pin widget (capless headphone) 0ch port c port c pin widget -- not available 0dh port d port d pin widget (class-d btl output) 0eh port e port e pin widget (line out (i2s)) 0fh port f port f pin widget (line in, mic) 10h monoout monoout pin widget (output only) 11h digmic0 digital microphone 0 pin widget 12h digmic1 vol vendor specific widget - d-mic1 volume (d pin to a mux connection) 13h dac0 stereo output converter to dac 14h dac1 stereo output converter to dac 15h adc0 stereo input converter to adc 16h adc1 stereo input converter to adc 17h adc0mux adc0 mux with volume and mute 18h adc1mux adc1 mux with volume and mute 19h mono_mux mono output source select 1ah mono_mix stereo to mono conversion 1bh mixer input mixer (input ports, dacs, analog pc_beep) 1ch mixeroutvol volume control for analog mixer 1dh spdifout0 stereo output for spdif_out 1eh spdifout1 second ster eo output for spdif_out 1fh dig0pin first digital output pin (pin48) 20h dig1pin second digital output pin / dmic input pin (pin 46) 21h pcbeep digital pc beep 22h vsw vendor defined widget
idt confidential 86 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.2. reset key abbreviation description por power on reset. safg single afg reset - one single write to the reset verb in the afg node. dafg double afg reset - two consecutive single afg resets with only idle frames (if any) and no link resets between. s&dafg single and double afg reset - either one will cause reset. lr link reset - level sensitive reset anytime the hda reset is set low. elr exiting link reset - edge sensitive reset any time the hda reset transitions from low to high. ulr unexpected link reset - level sensitive reset anytime the hda reset is set low when the clkstopok indicator is currently set to 0. ps power state change - reset anytime the actual power state changes for the widget in question. 7.3. root (nid = 00h): vendorid reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0000h field name bits r/w default reset vendor 31:16 r 111dh n/a vendor id. devicefix 15:8 r see below n/a device id. deviceprog 7:0 r see below n/a device id. device 92HD92 device id 76e2h
idt confidential 87 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.3.1. root (nid = 00h): revid reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0002h field name bits r/w default reset rsvd 31:24 r 00h n/a (hard-coded) reserved. major 23:20 r 1h n/a (hard-coded) major rev number of compliant hd audio spec. minor 19:16 r 0h n/a (hard-coded) minor rev number of compliant hd audio spec. revisionfix 15:12 r xh n/a (hard-coded) vendor's rev number for this device. revisionprog 11:8 r xh n/a (hard-coded) vendor's rev number for this device. steppingfix 7:4 r xh n/a (hard-coded) vendor stepping number within the vendor revid. steppingprog 3:0 r xh n/a (hard-coded) vendor stepping number within the vendor revid. 7.3.2. root (nid = 00h): nodeinfo reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0004h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved.
idt confidential 88 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo startnid 23:16 r 01h n/a (hard-coded) starting node number (nid) of first function group rsvd1 15:8 r 00h n/a (hard-coded) reserved. totalnodes 7:0 r 01h n/a (hard-coded) total number of nodes 7.4. afg (nid = 01h): nodeinfo reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0004h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. startnid 23:16 r 0ah n/a (hard-coded) starting node number for function group subordinate nodes. rsvd1 15:8 r 00h n/a (hard-coded) reserved. totalnodes 7:0 r 19h n/a (hard-coded) total number of nodes. 7.4.1. afg (nid = 01h): fgtype reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0005h field name bits r/w default reset
idt confidential 89 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo field name bits r/w default reset rsvd 31:9 r 000000h n/a (hard-coded) reserved. unsol 8 r 1h n/a (hard-coded) unsolicited response supported: 1 = yes, 0 = no. nodetype 7:0 r 1h n/a (hard-coded) function group type: 00h = reserved 01h = audio function group 02h = vendor defined modem function group 03h-7fh = reserved 80h-ffh = vendor defined function group 7.4.2. afg (nid = 01h): afgcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0008h field name bits r/w default reset rsvd3 31:17 r 00h n/a (hard-coded) reserved. beepgen 16 r 1h n/a (hard-coded) beep generator present: 1 = yes, 0 = no. rsvd2 15:12 r 0h n/a (hard-coded) reserved. inputdelay 11:8 r dh n/a (hard-coded) typical latency in frames. number of samples between when the sample is re- ceived as an analog signal at the pin and when the digital representation is transmitted on the hd audio link. rsvd1 7:4 r 0h n/a (hard-coded) reserved.
idt confidential 90 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo outputdelay 3:0 r dh n/a (hard-coded) typical latency in frames. number of samples between when the signal is re- ceived from the hd audio link and when it appears as an analog signal at the pin. 7.4.3. afg (nid = 01h): pcmcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000ah field name bits r/w default reset rsvd2 31:21 r 000h n/a (hard-coded) reserved. b32 20 r 0h n/a (hard-coded) 32 bit audio format support: 1 = yes, 0 = no. b24 19 r 1h n/a (hard-coded) 24 bit audio format support: 1 = yes, 0 = no. b20 18 r 1h n/a (hard-coded) 20 bit audio format support: 1 = yes, 0 = no. b16 17 r 1h n/a (hard-coded) 16 bit audio format support: 1 = yes, 0 = no. b8 16 r 0h n/a (hard-coded) 8 bit audio format support: 1 = yes, 0 = no. rsvd1 15:12 r 0h n/a (hard-coded) reserved. r12 11 r 0h n/a (hard-coded) 384khz rate support: 1 = yes, 0 = no. r11 10 r 1h n/a (hard-coded) 192khz rate support: 1 = yes, 0 = no. field name bits r/w default reset
idt confidential 91 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo r10 9 r 0h n/a (hard-coded) 176.4khz rate support: 1 = yes, 0 = no. r9 8 r 1h n/a (hard-coded) 96khz rate support: 1 = yes, 0 = no. r8 7 r 1h n/a (hard-coded) 88.2khz rate support: 1 = yes, 0 = no. r7 6 r 1h n/a (hard-coded) 48khz rate support: 1 = yes, 0 = no. r6 5 r 1h n/a (hard-coded) 44.1khz rate support: 1 = yes, 0 = no. r5 4 r 0h n/a (hard-coded) 32khz rate support: 1 = yes, 0 = no. r4 3 r 0h n/a (hard-coded) 22.05khz rate support: 1 = yes, 0 = no. r3 2 r 0h n/a (hard-coded) 16khz rate support: 1 = yes, 0 = no. r2 1 r 0h n/a (hard-coded) 11.025khz rate support: 1 = yes, 0 = no. r1 0 r 0h n/a (hard-coded) 8khz rate support: 1 = yes, 0 = no. 7.4.4. afg (nid = 01h): streamcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000bh field name bits r/w default reset
idt confidential 92 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo field name bits r/w default reset rsvd 31:3 r 00000000h n/a (hard-coded) reserved. ac3 2 r 0h n/a (hard-coded) ac-3 formatted data support: 1 = yes, 0 = no. float32 1 r 0h n/a (hard-coded) float32 formatted data support: 1 = yes, 0 = no. pcm 0 r 1h n/a (hard-coded) pcm-formatted data support: 1 = yes, 0 = no. 7.4.5. afg (nid = 01h): inampcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000dh field name bits r/w default reset mute 31 r 0h n/a (hard-coded) mute support: 1 = yes, 0 = no. rsvd3 30:23 r 00h n/a (hard-coded) reserved. stepsize 22:16 r 27h n/a (hard-coded) size of each step in the gain range: 0 to 127 = .25db to 32db, in .25db steps. rsvd2 15 r 0h n/a (hard-coded) reserved. numsteps 14:8 r 03h n/a (hard-coded) number of gains steps (number of possible settings - 1). rsvd1 7 r 0h n/a (hard-coded) reserved.
idt confidential 93 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo offset 6:0 r 00h n/a (hard-coded) indicates which step is 0db 7.4.6. afg (nid = 01h): pwrstatecap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000fh field name bits r/w default reset epss 31 r 1h n/a (hard-coded) extended power states support: 1 = yes, 0 = no. clkstop 30 r 1h n/a (hard-coded) d3 clock stop support: 1 = yes, 0 = no. s3d3coldsup 29 r 1h n/a (hard-coded) codec state intended during system s3 state: 1 = d3hot, 0 = d3cold. rsvd 28:5 r 000000h n/a (hard-coded) reserved. d3coldsup 4 r 1h n/a (hard-coded) d3cold power state support: 1 = yes, 0 = no. d3sup 3 r 1h n/a (hard-coded) d3 power state support: 1 = yes, 0 = no. d2sup 2 r 1h n/a (hard-coded) d2 power state support: 1 = yes, 0 = no. d1sup 1 r 1h n/a (hard-coded) d1 power state support: 1 = yes, 0 = no. d0sup 0 r 1h n/a (hard-coded) d0 power state support: 1 = yes, 0 = no. field name bits r/w default reset
idt confidential 94 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.4.7. afg (nid = 01h): gpiocnt reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0011h field name bits r/w default reset gpiwake 31 r 1h n/a (hard-coded) wake capability. assuming the wake enable mask controls are enabled, gpio's configured as inputs can cause a wake (generate a status change event on the link) when there is a change in level on the pin. gpiunsol 30 r 1h n/a (hard-coded) gpio unsolicited response support: 1 = yes, 0 = no. rsvd 29:24 r 00h n/a (hard-coded) reserved. numgpis 23:16 r 00h n/a (hard-coded) number of gpi pins supported by function group. numgpos 15:8 r 00h n/a (hard-coded) number of gpo pins supported by function group. numgpios 7:0 r 05h n/a (hard-coded) number of gpio pins supported by function group. 7.4.8. afg (nid = 01h): outampcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0012h field name bits r/w default reset mute 31 r 1h n/a (hard-coded) mute support: 1 = yes, 0 = no.
idt confidential 95 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo rsvd3 30:23 r 00h n/a (hard-coded) reserved. stepsize 22:16 r 02h n/a (hard-coded) size of each step in the gain range: 0 to 127 = .25db to 32db, in .25db steps. rsvd2 15 r 0h n/a (hard-coded) reserved. numsteps 14:8 r 7fh n/a (hard-coded) number of gains steps (number of possible settings - 1). rsvd1 7 r 0h n/a (hard-coded) reserved. offset 6:0 r 7fh n/a (hard-coded) indicates which step is 0db 7.4.9. afg (nid = 01h): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h field name bits r/w default reset rsvd3 31:11 r 000000h n/a (hard-coded) reserved. settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this function group have been reset. cleared by pwrstate 'get' to this widget. clkstopok 9 r 1h por - dafg - ulr bit clock can currently be removed: 1 = yes, 0 = no. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. field name bits r/w default reset
idt confidential 96 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo rsvd2 7 r 0h n/a (hard-coded) reserved. act 6:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3 r 0h n/a (hard-coded) reserved. set 2:0 rw 3h por - dafg - lr current power state setting for this widget. 7.4.10. afg (nid = 01h): unsolresp reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 708h get f0800h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. en 7 rw 0h por - dafg - ulr unsolicited response enable: 1 = enabled, 0 = disabled. rsvd1 6 r 0h n/a (hard-coded) reserved. tag 5:0 rw 00h por - dafg - ulr software programmable field returned in top six bits (31:26) of every unsolicit- ed response generated by this node. 7.4.11. afg (nid = 01h): gpio reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 715h get f1500h field name bits r/w default reset
idt confidential 97 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo field name bits r/w default reset rsvd 31:5 r 00000000h n/a (hard-coded) reserved. data4 4 rw 0h por - dafg - ulr data for gpio4. if this gpio bit is configured as sticky (edge-sensitive) input, it can be cleared by writing "0". for details of read back value, refer to hd audio spec. section 7.3.3.22 data3 3 rw 0h por - dafg - ulr data for gpio3. if this gpio bit is configured as sticky (edge-sensitive) input, it can be cleared by writing "0". for details of read back value, refer to hd audio spec. section 7.3.3.22 data2 2 rw 0h por - dafg - ulr data for gpio2. if this gpio bit is configured as sticky (edge-sensitive) input, it can be cleared by writing "0". for details of read back value, refer to hd audio spec. section 7.3.3.22 data1 1 rw 0h por - dafg - ulr data for gpio1. if this gpio bit is configured as sticky (edge-sensitive) input, it can be cleared by writing "0". for details of read back value, refer to hd audio spec. section 7.3.3.22 data0 0 rw 0h por - dafg - ulr data for gpio0. if this gpio bit is configured as sticky (edge-sensitive) input, it can be cleared by writing "0". for details of read back value, refer to hd audio spec. section 7.3.3.22 7.4.12. afg (nid = 01h): gpioen reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 716h get f1600h field name bits r/w default reset rsvd 31:5 r 00000000h n/a (hard-coded) reserved.
idt confidential 98 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo mask4 4 rw 0h por - dafg - ulr enable for gpio4: 0 = pin is disabled (hi-z state); 1 = pin is enabled; behavior determined by gpio direction control mask3 3 rw 0h por - dafg - ulr enable for gpio3: 0 = pin is disabled (hi-z state); 1 = pin is enabled; behavior determined by gpio direction control mask2 2 rw 0h por - dafg - ulr enable for gpio2: 0 = pin is disabled (hi-z state); 1 = pin is enabled; behavior determined by gpio direction control mask1 1 rw 0h por - dafg - ulr enable for gpio1: 0 = pin is disabled (hi-z state); 1 = pin is enabled; behavior determined by gpio direction control mask0 0 rw 0h por - dafg - ulr enable for gpio0: 0 = pin is disabled (hi-z state); 1 = pin is enabled; behavior determined by gpio direction control 7.4.13. afg (nid = 01h): gpiodir reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 717h get f1700h field name bits r/w default reset rsvd 31:5 r 00000000h n/a (hard-coded) reserved. control4 4 rw 0h por - dafg - ulr direction control for gpio4: 0 = gpio is configured as input; 1 = gpio is con- figured as output control3 3 rw 0h por - dafg - ulr direction control for gpio3: 0 = gpio is configured as input; 1 = gpio is con- figured as output field name bits r/w default reset
idt confidential 99 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo control2 2 rw 0h por - dafg - ulr direction control for gpio2: 0 = gpio is configured as input; 1 = gpio is con- figured as output control1 1 rw 0h por - dafg - ulr direction control for gpio1: 0 = gpio is configured as input; 1 = gpio is con- figured as output control0 0 rw 0h por - dafg - ulr direction control for gpio0: 0 = gpio is configured as input; 1 = gpio is con- figured as output 7.4.14. afg (nid = 01h): gpiowakeen reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 718h get f1800h field name bits r/w default reset rsvd 31:5 r 00000000h n/a (hard-coded) reserved. w4 4 rw 0h por - dafg - ulr wake enable for gpio4: 0 = wake-up event is disabled; 1 = when hd audio link is powered down (rst# is asserted), a wake-up event will trigger a status change request event on the link. w3 3 rw 0h por - dafg - ulr wake enable for gpio3: 0 = wake-up event is disabled; 1 = when hd audio link is powered down (rst# is asserted), a wake-up event will trigger a status change request event on the link. w2 2 rw 0h por - dafg - ulr wake enable for gpio2: 0 = wake-up event is disabled; 1 = when hd audio link is powered down (rst# is asserted), a wake-up event will trigger a status change request event on the link. field name bits r/w default reset
idt confidential 100 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo w1 1 rw 0h por - dafg - ulr wake enable for gpio1: 0 = wake-up event is disabled; 1 = when hd audio link is powered down (rst# is asserted), a wake-up event will trigger a status change request event on the link. w0 0 rw 0h por - dafg - ulr wake enable for gpio0: 0 = wake-up event is disabled; 1 = when hd audio link is powered down (rst# is asserted), a wake-up event will trigger a status change request event on the link. 7.4.15. afg (nid = 01h): gpiounsol reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 719h get f1900h field name bits r/w default reset rsvd 31:5 r 00000000h n/a (hard-coded) reserved. enmask4 4 rw 0h por - dafg - ulr unsolicited enable mask for gpio4. if set, and the unsolicited response con- trol for this widget has been enabled, an unsolicited response will be sent when gpio2 is configured as input and changes state. enmask3 3 rw 0h por - dafg - ulr unsolicited enable mask for gpio3. if set, and the unsolicited response con- trol for this widget has been enabled, an unsolicited response will be sent when gpio2 is configured as input and changes state. enmask2 2 rw 0h por - dafg - ulr unsolicited enable mask for gpio2. if set, and the unsolicited response con- trol for this widget has been enabled, an unsolicited response will be sent when gpio2 is configured as input and changes state. enmask1 1 rw 0h por - dafg - ulr unsolicited enable mask for gpio1. if set, and the unsolicited response con- trol for this widget has been enabled, an unsolicited response will be sent when gpio1 is configured as input and changes state. field name bits r/w default reset
idt confidential 101 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo enmask0 0 rw 0h por - dafg - ulr unsolicited enable mask for gpio0. if set, and the unsolicited response con- trol for this widget has been enabled, an unsolicited response will be sent when gpio0 is configured as input and changes state. 7.4.16. afg (nid = 01h): gpiosticky reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 71ah get f1a00h field name bits r/w default reset rsvd 31:5 r 00000000h n/a (hard-coded) reserved. mask4 4 rw 0h por - dafg - ulr gpio4 input type (when configured as input): 0 = non-sticky (level-sensitive); 1 = sticky (edge-sensitive). mask3 3 rw 0h por - dafg - ulr gpio3 input type (when configured as input): 0 = non-sticky (level-sensitive); 1 = sticky (edge-sensitive). mask2 2 rw 0h por - dafg - ulr gpio2 input type (when configured as input): 0 = non-sticky (level-sensitive); 1 = sticky (edge-sensitive). mask1 1 rw 0h por - dafg - ulr gpio1 input type (when configured as input): 0 = non-sticky (level-sensitive); 1 = sticky (edge-sensitive). mask0 0 rw 0h por - dafg - ulr gpio0 input type (when configured as input): 0 = non-sticky (level-sensitive); 1 = sticky (edge-sensitive). 7.4.17. afg (nid = 01h): subid reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 723h 722h 721h 720h field name bits r/w default reset
idt confidential 102 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo get f2300h / f2200h / f2100h / f2000h field name bits r/w default reset subsys3 31:24 rw 00h por subsystem id (byte 3) subsys2 23:16 rw 00h por subsystem id (byte 2) subsys1 15:8 rw 01h por subsystem id (byte 1) assembly 7:0 rw 00h por assembly id (not applicable to codec vendors). 7.4.18. afg (nid = 01h): gpioplrty reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 770h get f7000h field name bits r/w default reset rsvd 31:5 r 00000000h n/a (hard-coded) reserved. gp4 4 rw 1h por - dafg - ulr gpio4 polarity: if configured as output or non-sticky input: 0 = inverting 1 = non-inverting if configured as sticky input: 0 = falling edges will be detected 1 = rising edges will be detected 7.4.17. afg (nid = 01h): subid reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0)
idt confidential 103 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo gp3 3 rw 1h por - dafg - ulr gpio3 polarity: if configured as output or non-sticky input: 0 = inverting 1 = non-inverting if configured as sticky input: 0 = falling edges will be detected 1 = rising edges will be detected gp2 2 rw 1h por - dafg - ulr gpio2 polarity: if configured as output or non-sticky input: 0 = inverting 1 = non-inverting if configured as sticky input: 0 = falling edges will be detected 1 = rising edges will be detected gp1 1 rw 1h por - dafg - ulr gpio1 polarity: if configured as output or non-sticky input: 0 = inverting 1 = non-inverting if configured as sticky input: 0 = falling edges will be detected 1 = rising edges will be detected gp0 0 rw 1h por - dafg - ulr gpio0 polarity: if configured as output or non-sticky input: 0 = inverting 1 = non-inverting if configured as sticky input: 0 = falling edges will be detected 1 = rising edges will be detected 7.4.19. afg (nid = 01h): gpiodrive reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 771h get f7100h field name bits r/w default reset
idt confidential 104 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo field name bits r/w default reset rsvd 31:5 r 00000000h n/a (hard-coded) reserved. od4 4 rw 0h por - dafg - ulr gpio4 drive mode: 0 = push-pull (drive 0 and 1); 1 = open drain (drive 0, float for 1). od3 3 rw 0h por - dafg - ulr gpio3 drive mode: 0 = push-pull (drive 0 and 1); 1 = open drain (drive 0, float for 1). od2 2 rw 0h por - dafg - ulr gpio2 drive mode: 0 = push-pull (drive 0 and 1); 1 = open drain (drive 0, float for 1). od1 1 rw 0h por - dafg - ulr gpio1 drive mode: 0 = push-pull (drive 0 and 1); 1 = open drain (drive 0, float for 1). od0 0 rw 0h por - dafg - ulr gpio0 drive mode: 0 = push-pull (drive 0 and 1); 1 = open-drain (drive 0, float for 1). 7.4.20. afg (nid = 01h): dmic reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 778h get f7800h field name bits r/w default reset rsvd 31:6 r 0000000h n/a (hard-coded) reserved. mono1 5 rw 0h por dmic1 mono select: 0 = stereo operati on, 1 = mono operation (left channel du- plicated to the right channel).
idt confidential 105 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo mono0 4 rw 0h por dmic0 mono select: 0 = stereo operati on, 1 = mono operation (left channel du- plicated to the right channel). phadj 3:2 rw 0h por selects what phase of the dmic clock the data should be latched: 0h = left data rising edge/right data falling edge 1h = left data center of high/right data center of low 2h = left data falling edge/right data rising edge 3h = left data center of low/right data center of high rate 1:0 rw 2h por selects the dmic clock rate: 0h = 4.704mhz 1h = 3.528mhz 2h = 2.352mhz 3h = 1.176mhz. 7.4.21. afg (nid = 01h): dacmode reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 780h get f8000h field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. swapen 8 rw 0h por internal dac left channel and right channel swap. 0h = not swap, 1h = swap. sdmsettledisable 7 rw 0h por sdm wait-to-settle disable: 1 = at mute, the sdm switches to the mute pattern immediately 0 = at mute, the sdm switches to the mute pattern after settling (can take up to ~45ms) field name bits r/w default reset
idt confidential 106 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo sdmcoeffsel 6 rw 0h por dac sdm coefficient select (stages 1, 2, 3): 1 = 1/16, 1/2, 1/4 0 = 1/16, 1/4, 1/2 sdmlfhalf 5 rw 0h por dac sdm local feedback coefficient select: 1 = 1/4096, 0 = 1/2048. sdmlfdisable 4 rw 0h por dac sdm local feedback disable: 1 = local feedback disabled, 0 = local feed- back enabled. invertvalid 3 rw 0h por dac valid invert: 1 = 7.056mhz valid strobe is inverted, 0 = 7.056mhz valid strobe is not inverted. invertdata 2 rw 0h por dac data invert: 1 = 1-bit outputs are inverted, 0 = 1-bit outputs are not invert- ed. atten6dbdisable 1 rw 1h por disable built-in -6db digital attenuation: 1 = -6db disabled, 0 = -6db enabled. fade 0 rw 1h por dac gain fade enable: 1 = gain will be slowly faded from old value to new value (~10ms) 0 = gain will jump immediately to new value. 7.4.22. afg (nid = 01h): adcmode reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 784h get f8400h field name bits r/w default reset rsvd2 31:4 r 0000000h n/a (hard-coded) reserved. field name bits r/w default reset
idt confidential 107 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo invertvalid 3 rw 0h por adc valid invert: 1 = 14.112mhz valid strobe is inverted, 0 = 14.112mhz valid strobe is not inverted. invertdata 2 rw 0h por adc data invert: 1 = 1-bit inputs are inverted, 0 = 1-bit inputs are not inverted. adcclkdelay 1 rw 0h por delay adc clock. dacclkdelay 0 rw 0h por delay dac clock. 7.4.23. afg (nid = 01h): portuse reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 7c0h get fc000h field name bits r/w default reset rsvd 31:7 r 0000000h n/a (hard-coded) reserved. mono 6 rw 1h por 1=power down port if not input or output enabled, 0=do not force power down based on input or output enable portf 5 rw 1h por 1=power down port if not input or output enabled, 0=do not force power down based on input or output enable porte 4 rw 1h por 1=power down port if not input or output enabled, 0=do not force power down based on input or output enable portd 3 rw 1h por 1=power down port if not input or output enabled, 0=do not force power down based on input or output enable. field name bits r/w default reset
idt confidential 108 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo portc 2 rw 1h por 1=power down port if not input or output enabled, 0=do not force power down based on input or output enable portb 1 rw 1h por 1=power down port if not input or output enabled, 0=do not force power down based on input or output enable porta 0 rw 1h por 1=power down port if not input or output enabled, 0=do not force power down based on input or output enable. 7.4.24. afg (nid = 01h): comjack reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 7c7h 7c6h get fc700h/fc600h field name bits r/w default reset rsvd3 31:14 r 00000000h n/a (hard-coded) reserved. debouncetime 13:12 rw 1h por combo jack debounce time set. 2'h0 = 0.1ms; 2'h1 = 125ms; 2'h2 = 500ms; 2'h3 = 1s." rsvd2 11 r oh n/a (hard-coded) reserved. rbcon 10:8 rw 4h por combo jack detection reference voltage 000 = 0.18*avdd 001 = 0.16*avdd 010 = 0.14*avdd 011 = 0.12*avdd 100 = 0.10*avdd 101 = 0.08*avdd 110 = 0.06*avdd 111 = 0.04*avdd field name bits r/w default reset
idt confidential 109 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo masterport 7:5 rw 0h por port tied to the jack presence detection switch 000 = port a 001 = port b 010 = port c 011 = port d 100 = port e 101 = port f rsvd1 4 r 0h n/a (hard-coded) reserved. slaveport 3:1 rw 0h por port used as microphone input when combo jack detection is enabled, port presence detection as shown in the pin complex is not sensed directly by the sense input but is inferred by the load placed on the vref_output associated with the port 000 = port a 001 = port b 010 = port c 011 = port d;100 = port e 101 = port f det-en 0 r 0h por 0h = disable combo jact detection 1h = enable combo jact detection 7.4.25. afg (nid = 01h): vspwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 7d8h get fd800h field name bits r/w default reset rsvd 31:2 r 00000000h n/a (hard-coded) reserved. field name bits r/w default reset
idt confidential 110 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo d5 1 rw 0h por - elr vendor specific d5 power state, only entered once the part is already in d3cold (this bit must be set before the command to enter d3cold). if set, this bit over- rides the d4 bit (bit 0). includes the power savings of d4, but additionally pow- ers down gpio pins, the vag amp, and the hp amps. exits this power state via por or rising edge of link reset. d4 0 rw 0h por - elr vendor specific d4 power state, only entered once the part is already in d3cold (this bit must be set before the command to enter d3cold). if the d5 bit (bit 1) is set, this bit is overridden. includes the power savings of d3cold, but addi- tionally powers down the hda interface (no responses). exit this power state via por or rising edge of link reset. 7.4.26. afg (nid = 01h): anaport reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 7edh 7ech get fec00h field name bits r/w default reset rsvd2 31:7 r 0000000h n/a (hard-coded) reserved. monopwd 6 rw 0h por power down mono output. fpwd 5 rw 0h por power down port f. epwd 4 rw 0h por power down port e. dpwd 3 rw 0h por power down port d. cpwd 2 rw 0h por power down port c. field name bits r/w default reset
idt confidential 111 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo bpwd 1 rw 0h por power down port b. apwd 0 rw 0h por power down port a. 7.4.27. afg (nid = 01h): anabtl reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 7f6h 7f5h 7f4h get ff400h field name bits r/w default reset rsvd6 31:22 r 0h n/a (hard-coded) reserved. scstabletimesel 21:22 rw 0h por the programmed time window for short circuit detect. this is available on wb silicon revisi ons and beyond. prior silicon revi- sions, these bits are reserved. tsoverridehiz 19 rw 0h por override hiz for the btl amplifier power stage circuit: set to 1 to hiz, set back to 0 to normal mode tstestmode 18 rw 0h por temp sense test mode select, 0=normal operation, 1=sensor will trip at ambi- ent temperature. tsforcepwd 17 rw 1h por temp sense force powerdown select 0=btl will not be muted and powered down even if it is still overheating when the volume is 0h 1=btl will be muted and powered down even if it is still overheating when the volume is 0h tsinstantcutmode 16 rw 0h por temp sense instant cut mode 0=two trip points used to smoothly adjust the volume 1=one single trip point used to set volume to wither 0 or max value (ti mode) field name bits r/w default reset
idt confidential 112 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo tswait 15:12 rw 3h por temperature sensing wait time between volume increments 0h = 2ms (polling at 2ms) 1h = 4ms (polling at 4ms) 2h = 8ms (polling at 8ms) 3h = 16ms (polling at 16ms) 4h = 32ms (polling at 16ms) 5h = 64ms (polling at 16ms) 6h = 128ms (polling at 16ms) 7h = 256ms (polling at 16ms) 8h = 512ms (polling at 16ms) 9h = 1.024s (polling at 16ms) ah = 2.048s (polling at 16ms) bh = 4.096s (polling at 16ms) ch = 8.192s (polling at 16ms) dh = 16.384s (polling at 16ms) eh = 32.768s (polling at 16ms) fh = 65.536s (polling at 16ms). tstriphish 11:9 rw 3h por temp sense high trip point setting: 0h = 125 degrees c 1h =140 degrees c 2h = 155 degrees c 3h = 170 degrees c 4h = 185 c 5h = 200 c 6h = 215 c 7h = reserved tsoverriderest 8 rw 0h por override reset for the btl amplifier temp se nse circuit: set to 1 to recalculate, set back to 0 to latch the value tstriplow 7:5 rw 2h por temp sense low trip point setting: 0h = 110 degrees c 1h = 125 degrees c 2h = 140 degrees c 3h = 155 degrees c 4h = 170 c 5h = 185 c 6h = 200 c 7h = 215 c rsvd1 4:0 r 0h na reserved field name bits r/w default reset
idt confidential 113 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.4.28. afg (nid = 01h): anabtlstatus reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get ff700h field name bits r/w default reset rsvd 31:20 r 00h n/a (hard-coded) reserved. tstriphigh 19 r 0h por temp sense high trip point status tstriplow 18 r 0h por temp sense low trip point status tsmute 17 r 0h por temp sense forced mute status for btl amplifier tspwd 16 r 0h por temp sense forced powerdown status for btl amplifier tsleftvol 15:8 r 0h por temp sense volume status for the btl amplifier: 00000000b..11111111b = range specified for spkvol field. tsrightvol 7:0 r 0h por temp sense volume status for the btl amplifier: 00000000b..11111111b = range specified for spkvol field. 7.4.29. afg (nid = 01h): anacapless reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 7fah 7f9h 7f8h get ff800h
idt confidential 114 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo field name bits r/w default reset rsvd2 31:26 r 00h n/a (hard-coded) reserved. vregscdet 25 r 0h por capless regulator short circuit detect indicator. chargepumpscdet 24 r 0h por capless charge pump short circuit detect indicator. vregsel 23:20 rw 5h por capless regulator output voltage multiply ratio bits [3..2] reserved bits [1..0]: 00b = 2*vbg 01b = 2.1*vbg 10b = 2.2*vbg 11b = 2.3*vbg vregscrstb 19 rw 0h por capless regulator short circuit detect rese t: 0 = short circuit detect disabled, 1 = short circuit detect enabled. vreggndshort 18 rw 0h por ground the capless regulator output. vregpwd 17 rw 0h por capless regulator powerdown. chargepumpscrstb 16 rw 0h por capless charge pump short circuit detect reset: 0 = short circuit detect dis- abled, 1 = short circuit detect enabled. chargepumphiz 15 rw 0h por hi-z the capless charge pump outputs. chargepumppwd 14 rw 0h por capless charge pump powerdown. chargepumpsplydetover- ride 13 rw 0h por capless charge pump supply detect override.
idt confidential 115 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo chargepumpfreqbypass 12 rw 1h por capless charge pump frequency reg bypass. chargepumpclkrate 11:8 rw 8h por capless charge pump clock rate: 0000b = 800.0khz (24mhz/30) 0001b = 750.0khz (24mhz/32) 0010b = 706.9khz (24mhz/34) 0011b = 666.7khz (24mhz/36) 0100b = 631.6khz (24mhz/38) 0101b = 600.0khz (24mhz/40) 0110b = 571.4khz (24mhz/42) 0111b = 545.5khz (24mhz/44) 1000b = 800.0khz (24mhz/30) 1001b = 857.1khz (24mhz/28) 1010b = 923.1khz (24mhz/26) 1011b = 1.000mhz (24mhz/24) 1100b = 1.091mhz (24mhz/22) 1101b = 1.200mhz (24mhz/20) 1110b = 1.333mhz (24mhz/18) 1111b = 1.500mhz (24mhz/16) chargepumpclkdiv 7:5 rw 4h por capless charge pump analog clock divider: 001b = no divide 010b = divide by 2, 50% duty cycle 100b = divide by 4, 50% duty cycle 110b = divide by 2, 75% duty cycle 011b = divide by 4, 75% duty cycle 111b = divide by 4, 87.5% duty cycle other values undefined chargepumpclksel 4 rw 0h por capless charge pump clock select: 0 = ring oscillator, 1 = charge pump clock defined by afgcaplesschargepumpclkrate[3:0] field below. padgnd 3 rw 0h por ground the output pad of the capless amplifiers. inputgnd 2 rw 0h por ground the input to the capless output amplifiers. rsvd1 1 r 0h na reserved field name bits r/w default reset
idt confidential 116 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo antipopbypass 0 rw 0h por 0 = enable anti-pop on the capless headphone; 1 = bypass anti-pop on the ca- pless headphone. 7.4.30. afg (nid = 01h): reset reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 7ffh get fff00h field name bits r/w default reset rsvd1 31:8 r 000000h n/a (hard-coded) reserved. execute 7:0 w 00h n/a (hard-coded) function reset. function group reset is executed when the set verb 7ff is written with 8-bit payload of 00h. the codec should issue a response to ac- knowledge receipt of the verb, and then reset the affected function group and all associated widgets to their power-on reset values. some controls such as configuration default controls should not be reset. overlaps response. field name bits r/w default reset
idt confidential 117 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.4.31. afg (nid = 01h): dac3outamp (mono out volume) reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 7b6hh get fb600h field name bits r/w default reset rsvd 31:8 r 0000000h n/a (hard-coded) reserved. mute 7 rw 0h por - dafg - ulr amp mute: 1 = muted, 0 = not muted gain 6:0 rw 7fh por - dafg - ulr amp gain step number (see outampcap parameter of afg)
idt confidential 118 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.4.32. afg (nid = 01h): dac5outampleft (auxmode) reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 7b7hh get fb700h field name bits r/w default reset rsvd 31:8 r 0000000h n/a (hard-coded) reserved. mute 7 rw 0h por - dafg - ulr amp mute: 1 = muted, 0 = not muted gain 6:0 rw 7fh por - dafg - ulr amp gain step number (see outampcap parameter of afg) 7.4.33. afg (nid = 01h): dac5outampright (auxmode) reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 7b8hh get fb800h field name bits r/w default reset rsvd 31:8 r 0000000h n/a (hard-coded) reserved. mute 7 rw 0h por - dafg - ulr amp mute: 1 = muted, 0 = not muted gain 6:0 rw 7fh por - dafg - ulr amp gain step number (see outampcap parameter of afg) 7.4.34. afg (nid = 01h): adc4outampleft (auxmode) reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 7b9hh get fb900h
idt confidential 119 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo field name bits r/w default reset rsvd 31:8 r 0000000h n/a (hard-coded) reserved. mute 7 rw 0h por - dafg - ulr amp mute: 1 = muted, 0 = not muted gain 6:0 rw 10h por - dafg - ulr amp gain step number (see outampcap parameter of afg) 7.4.35. afg (nid = 01h): adc4outampright (auxmode) reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 7bahh get fba00h field name bits r/w default reset rsvd 31:8 r 0000000h n/a (hard-coded) reserved. mute 7 rw 0h por - dafg - ulr amp mute: 1 = muted, 0 = not muted gain 6:0 rw 10h por - dafg - ulr amp gain step number (see outampcap parameter of afg)
idt confidential 120 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.4.36. afg (nid = 01h): i2sctrl reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 7c8h get fc800h field name bits r/w default reset rsvd2 31:6 r 0000000h n/a (hard-coded) reserved. forceportf2spdif0 5 rw 0h por force i2s input to portf to spdifout0 for test purpose rsvd1 4 r 0h n/a (hard-coded) reserved. forceportf2portb 3 rw 0h por in i2s mode, the dac2 output is routed to portb to verified dac2 i2cdebug 2 rw 0h por i2c bus debug mode bitexactseldac 1 rw 0h por i2s bit exact mode select data source. 0h = data from dac0, 1h = data from dac1. bitexact 0 rw 0h por 0h = disable i2s bit exact mode 1h = enable i2s exact mode.
idt confidential 121 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.4.37. afg (nid = 01h): eapd reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 788h get f8800h field name bits r/w default reset rsvd5 31:19 r 00000h n/a (hard-coded) reserved. hpesdinv 18 rw 0h por port e hp amp shutdown invert: 0 = amp will power down (or mute) when eapd pin is low 1 = amp will power down (or mute) when eapd pin is high hpesdmode 17 rw 1h por port e hp amp shutdown mode: 0 = amp will mute when disabled 1 = amp will enter a low power state when disabled hpesd 16 rw 0h por port e hp amp shutdown control select: 0 = amp controlled by eapd pin only 1 = amp controlled by power state only rsvd4 15 r 0 n/a (hard-coded) reserved. hpbsdinv 14 rw 0h por port b hp amp shutdown invert: 0 = amp will power down (or mute) when eapd pin is low 1 = amp will power down (or mute) when eapd pin is high hpbsdmode 13 rw 1h por port b hp amp shutdown mode: 0 = amp will mute when disabled 1 = amp will enter a low power state when disabled hpbsd 12 rw 0h por port b hp amp shutdown control select: 0 = amp controlled by eapd pin only 1 = amp controlled by power state only
idt confidential 122 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo rsvd3 11 r 0h n/a (hard-coded) reserved. hpasdinv 10 rw 0h por port a hp amp shutdown invert: 0 = amp will power down (or mute) when eapd pin is low 1 = amp will power down (or mute) when eapd pin is high hpasdmode 9 rw 1h por port a hp amp shutdown mode: 0 = amp will mute when disabled 1 = amp will enter a low power state when disabled hpasd 8 rw 0h por port a hp amp shutdown control select: 0 = amp controlled by eapd pin only 1 = amp controlled by power state only rsvd2 7 r 0h n/a (hard-coded) reserved. btlsdinv 6 rw 0h por btl amp shutdown invert: 0 = amp will power down (or mute) when eapd pin is low 1 = amp will power down (or mute) when eapd pin is high btlsdmode 5 rw 1h por btl amp shutdown mode: 0 = amp will mute when disabled 1 = amp will enter a low power state when disabled btlsd 4 rw 0h por btl amp shutdown control select: 0 = amp controlled by eapd pin only 1 = amp controlled by power state only rsvd1 3:2 r 0h n/a (hard-coded) reserved. pinmode 1:0 rw 0h por eapd pin mode: 00b = open drain i/o (value at pin is wi red-and of eapd bit & external signal) 01b = cmos output (value of eapd bit is forced at pin) 1xb = cmos input (external signal cont rols internal amps, eapd bit ignored) field name bits r/w default reset
idt confidential 123 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.5. porta (nid = 0ah): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. type 23:20 r 4h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined delay 19:16 r 0h n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 0h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no. dig 9 r 0h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). connlist 8 r 1h n/a (hard-coded) connection list present: 1 = yes, 0 = no. unsolcap 7 r 1h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no.
idt confidential 124 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo procwidget 6 r 0h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. formatovrd 4 r 0h n/a (hard-coded) stream format override: 1 = yes, 0 = no. ampparovrd 3 r 0h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 0h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 1h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 1h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). 7.5.1. porta (nid = 0ah): pincap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000ch field name bits r/w default reset rsvd2 31:17 r 0000h n/a (hard-coded) reserved. eapdcap 16 r 1h n/a (hard-coded) eapd support: 1 = yes, 0 = no. field name bits r/w default reset
idt confidential 125 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo vrefcntrl 15:8 r 17h n/a (hard-coded) vref support: bit 7 = reserved bit 6 = reserved bit 5 = 100% support (1 = yes, 0 = no) bit 4 = 80% support (1 = yes, 0 = no) bit 3 = reserved bit 2 = gnd support (1 = yes, 0 = no) bit 1 = 50% support (1 = yes, 0 = no) bit 0 = hi-z support (1 = yes, 0 = no) rsvd1 7 r 0h n/a (hard-coded) reserved. balancedio 6 r 0h n/a (hard-coded) balanced i/o support: 1 = yes, 0 = no. incap 5 r 1h n/a (hard-coded) input support: 1 = yes, 0 = no. outcap 4 r 1h n/a (hard-coded) output support: 1 = yes, 0 = no. hdphdrvcap 3 r 1h n/a (hard-coded) headphone amp present: 1 = yes, 0 = no. presdtctcap 2 r 1h n/a (hard-coded) presence detection support: 1 = yes, 0 = no. trigrqd 1 r 0h n/a (hard-coded) trigger required for impedance sense: 1 = yes, 0 = no. impsensecap 0 r 0h n/a (hard-coded) impedance sense support: 1 = yes, 0 = no. 7.5.2. porta (nid = 0ah): conlst reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000eh field name bits r/w default reset
idt confidential 126 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. lform 7 r 0h n/a (hard-coded) connection list format: 1 = long-form (15-bi t) nid entries, 0 = short-form (7-bit) nid entries. conl 6:0 r 03h n/a (hard-coded) number of nid entries in connection list. 7.5.3. porta (nid = 0ah): conlstentry0 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0200h field name bits r/w default reset conl3 31:24 r 00h n/a (hard-coded) dac2 converter widget (0x22) conl2 23:16 r 1ch n/a (hard-coded) mixeroutvol selector widget (0x1c) conl1 15:8 r 14h n/a (hard-coded) dac1 converter widget (0x14) conl0 7:0 r 13h n/a (hard-coded) dac0 converter widget (0x13) 7.5.4. porta (nid = 0ah): inampleft reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 360h get b2000h
idt confidential 127 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo field name bits r/w default reset rsvd1 31:2 r 00000000h n/a (hard-coded) reserved. gain 1:0 rw 0h por - dafg - ulr amp gain step number (see inampcap param eter pertaining to this widget). 7.5.5. porta (nid = 0ah): inampright reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 350h get b0000h field name bits r/w default reset rsvd1 31:2 r 00000000h n/a (hard-coded) reserved. gain 1:0 rw 0h por - dafg - ulr amp gain step number (see inampcap param eter pertaining to this widget). 7.5.6. porta (nid = 0ah): conselectctrl reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 701h get f0100h field name bits r/w default reset rsvd 31:2 r 00000000h n/a (hard-coded) reserved. index 1:0 rw 0h por - dafg - ulr connection select control index.
idt confidential 128 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.5.7. porta (nid = 0ah): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved. settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. act 5:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved. set 1:0 rw 0h por - dafg - lr current power state setting for this widget. 7.5.8. porta (nid = 0ah): pinwcntrl reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 707h get f0700h
idt confidential 129 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. hphnen 7 rw 0h por - dafg - ulr headphone amp enable: 1 = enabled, 0 = disabled. outen 6 rw 0h por - dafg - ulr output enable: 1 = enabled, 0 = disabled. inen 5 rw 0h por - dafg - ulr input enable: 1 = enabled, 0 = disabled. rsvd1 4:3 r 0h n/a (hard-coded) reserved. vrefen 2:0 rw 0h por - dafg - ulr vref selection (see vrefcntrl field of pincap parameter for supported selec- tions): 000b= hi-z 001b= 50% 010b= gnd 011b= reserved 100b= 80% 101b= 100% 110b= reserved 111b= reserved 7.5.9. porta (nid = 0ah): unsolresp reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 708h get f0800h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved.
idt confidential 130 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo en 7 rw 0h por - dafg - ulr unsolicited response enable (also enables wake events for this widget): 1 = enabled, 0 = disabled. rsvd1 6 r 0h n/a (hard-coded) reserved. tag 5:0 rw 00h por - dafg - ulr software programmable field returned in top six bits (31:26) of every unsolicit- ed response generated by this node. 7.5.10. porta (nid = 0ah): chsense reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 709h get f0900h field name bits r/w default reset presdtct 31 r 0h por presence detection indicator: 1 = presence detected; 0 = presence not detect- ed. rsvd 30:0 r 00000000h n/a (hard-coded) reserved. 7.5.11. porta (nid = 0ah): eapdbtllr reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 70ch get f0c00h field name bits r/w default reset rsvd2 31:2 r 00000000h n/a (hard-coded) reserved. field name bits r/w default reset
idt confidential 131 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo eapd 1 rw 1h por - dafg - ulr eapd control: 1 = set eapd pin to 1 (powered) up if this pin is powered up, 0 = set eapd pin to 0. rsvd1 0 r 0h n/a (hard-coded) reserved. 7.5.12. porta (nid = 0ah): configdefault reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 71fh 71eh 71dh 71ch get f1f00h / f1e00h / f1d00h / f1c00h field name bits r/w default reset portconnectivity 31:30 rw 0h por port connectivity: 0h = port complex is connected to a jack 1h = no physical connection for port 2h = fixed function device is attached 3h = both jack and internal device attached (info in all other fields refers to in- tegrated device, any presence detection refers to jack) location 29:24 rw 02h por location bits [5..4]: 0h = external on primary chassis 1h = internal 2h = separate chassis 3h = other bits [3..0]: 0h = n/a 1h = rear 2h = front 3h = left 4h = right 5h = top 6h = bottom 7h-9h = special ah-fh = reserved field name bits r/w default reset
idt confidential 132 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo device 23:20 rw ah por default device: 0h = line out 1h = speaker 2h = hp out 3h = cd 4h = spdif out 5h = digital other out 6h = modem line side 7h = modem handset side 8h = line in 9h = aux ah = mic in bh = telephony ch = spdif in dh = digital other in eh = reserved fh = other connectiontype 19:16 rw 1h por connection type: 0h = unknown 1h = 1/8" stereo/mono 2h = 1/4" stereo/mono 3h = atapi internal 4h = rca 5h = optical 6h = other digital 7h = other analog 8h = multichannel analog (din) 9h = xlr/professional ah = rj-11 (modem) bh = combination ch-eh = reserved fh = other field name bits r/w default reset
idt confidential 133 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo color 15:12 rw 9h por color: 0h = unknown 1h = black 2h = grey 3h = blue 4h = green 5h = red 6h = orange 7h = yellow 8h = purple 9h = pink ah-dh = reserved eh = white fh = other misc 11:8 rw 0h por miscellaneous: bits [3..1] = reserved bit 0 = jack detect override association 7:4 rw 2h por default assocation. sequence 3:0 rw fh por sequence. 7.6. portb (nid = 0bh): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. field name bits r/w default reset
idt confidential 134 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo type 23:20 r 4h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined delay 19:16 r 0h n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 0h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no. dig 9 r 0h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). connlist 8 r 1h n/a (hard-coded) connection list present: 1 = yes, 0 = no. unsolcap 7 r 1h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no. procwidget 6 r 0h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. formatovrd 4 r 0h n/a (hard-coded) stream format override: 1 = yes, 0 = no. field name bits r/w default reset
idt confidential 135 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo ampparovrd 3 r 0h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 0h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 0h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 1h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). 7.6.1. portb (nid = 0bh): pincap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000ch field name bits r/w default reset rsvd2 31:17 r 0000h n/a (hard-coded) reserved. eapdcap 16 r 1h n/a (hard-coded) eapd support: 1 = yes, 0 = no. vrefcntrl 15:8 r 00h n/a (hard-coded) vref support: bit 7 = reserved bit 6 = reserved bit 5 = 100% support (1 = yes, 0 = no) bit 4 = 80% support (1 = yes, 0 = no) bit 3 = reserved bit 2 = gnd support (1 = yes, 0 = no) bit 1 = 50% support (1 = yes, 0 = no) bit 0 = hi-z support (1 = yes, 0 = no) rsvd1 7 r 0h n/a (hard-coded) reserved. field name bits r/w default reset
idt confidential 136 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo balancedio 6 r 0h n/a (hard-coded) balanced i/o support: 1 = yes, 0 = no. incap 5 r 0h n/a (hard-coded) input support: 1 = yes, 0 = no. outcap 4 r 1h n/a (hard-coded) output support: 1 = yes, 0 = no. hdphdrvcap 3 r 1h n/a (hard-coded) headphone amp present: 1 = yes, 0 = no. presdtctcap 2 r 1h n/a (hard-coded) presence detection support: 1 = yes, 0 = no. trigrqd 1 r 0h n/a (hard-coded) trigger required for impedance sense: 1 = yes, 0 = no. impsensecap 0 r 0h n/a (hard-coded) impedance sense support: 1 = yes, 0 = no. 7.6.2. portb (nid = 0bh): conlst reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000eh field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. lform 7 r 0h n/a (hard-coded) connection list format: 1 = long-form (15-bi t) nid entries, 0 = short-form (7-bit) nid entries. conl 6:0 r 03h n/a (hard-coded) number of nid entries in connection list. field name bits r/w default reset
idt confidential 137 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.6.3. portb (nid = 0bh): conlstentry0 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0200h field name bits r/w default reset conl3 31:24 r 00h n/a (hard-coded) dac2 converter widget (0x22) conl2 23:16 r 1ch n/a (hard-coded) mixeroutvol selector widget (0x1c) conl1 15:8 r 14h n/a (hard-coded) dac1 converter widget (0x14) conl0 7:0 r 13h n/a (hard-coded) dac0 converter widget (0x13) 7.6.4. portb (nid = 0bh): conselectctrl reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 701h get f0100h field name bits r/w default reset rsvd 31:2 r 00000000h n/a (hard-coded) reserved. index 1:0 rw 0h por - dafg - ulr connection select control index. 7.6.5. portb (nid = 0bh): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h
idt confidential 138 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved. settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. act 5:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved. set 1:0 rw 0h por - dafg - lr current power state setting for this widget. 7.6.6. portb (nid = 0bh): pinwcntrl reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 707h get f0700h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. hphnen 7 rw 0h por - dafg - ulr headphone amp enable: 1 = enabled, 0 = disabled.
idt confidential 139 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo outen 6 rw 0h por - dafg - ulr output enable: 1 = enabled, 0 = disabled. rsvd1 5:0 rw 00h n/a (hard-coded) reserved. 7.6.7. portb (nid = 0bh): unsolresp reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 708h get f0800h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. en 7 rw 0h por - dafg - ulr unsolicited response enable (also enables wake events for this widget): 1 = enabled, 0 = disabled. rsvd1 6 r 0h n/a (hard-coded) reserved. tag 5:0 rw 00h por - dafg - ulr software programmable field returned in top six bits (31:26) of every unsolicit- ed response generated by this node. 7.6.8. portb (nid = 0bh): chsense reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 709h get f0900h field name bits r/w default reset
idt confidential 140 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo field name bits r/w default reset presdtct 31 r 0h por presence detection indicator: 1 = presence detected; 0 = presence not detect- ed. rsvd 30:0 r 00000000h n/a (hard-coded) reserved. 7.6.9. portb (nid = 0bh): eapdbtllr reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 70ch get f0c00h field name bits r/w default reset rsvd2 31:2 r 00000000h n/a (hard-coded) reserved. eapd 1 rw 1h por - dafg - ulr eapd control: 1 = set eapd pin to 1 (powered) up if this pin is powered up, 0 = set eapd pin to 0. rsvd1 0 r 0h n/a (hard-coded) reserved. 7.6.10. portb (nid = 0bh): configdefault reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 71fh 71eh 71dh 71ch get f1f00h / f1e00h / f1d00h / f1c00h
idt confidential 141 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo field name bits r/w default reset portconnectivity 31:30 rw 0h por port connectivity: 0h = port complex is connected to a jack 1h = no physical connection for port 2h = fixed function device is attached 3h = both jack and internal device attached (info in all other fields refers to in- tegrated device, any presence detection refers to jack) location 29:24 rw 02h por location bits [5..4]: 0h = external on primary chassis 1h = internal 2h = separate chassis 3h = other bits [3..0]: 0h = n/a 1h = rear 2h = front 3h = left 4h = right 5h = top 6h = bottom 7h-9h = special ah-fh = reserved device 23:20 rw 2h por default device: 0h = line out 1h = speaker 2h = hp out 3h = cd 4h = spdif out 5h = digital other out 6h = modem line side 7h = modem handset side 8h = line in 9h = aux ah = mic in bh = telephony ch = spdif in dh = digital other in eh = reserved fh = other
idt confidential 142 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo connectiontype 19:16 rw 1h por connection type: 0h = unknown 1h = 1/8" stereo/mono 2h = 1/4" stereo/mono 3h = atapi internal 4h = rca 5h = optical 6h = other digital 7h = other analog 8h = multichannel analog (din) 9h = xlr/professional ah = rj-11 (modem) bh = combination ch-eh = reserved fh = other color 15:12 rw 4h por color: 0h = unknown 1h = black 2h = grey 3h = blue 4h = green 5h = red 6h = orange 7h = yellow 8h = purple 9h = pink ah-dh = reserved eh = white fh = other misc 11:8 rw 0h por miscellaneous: bits [3..1] = reserved bit 0 = jack detect override association 7:4 rw 1h por default assocation. sequence 3:0 rw fh por sequence. field name bits r/w default reset
idt confidential 143 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.7. (nid = 0ch): vendor reserved
idt confidential 144 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.8. portd (nid = 0dh): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. type 23:20 r 4h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined delay 19:16 r 0h n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 0h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no. dig 9 r 0h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). connlist 8 r 1h n/a (hard-coded) connection list present: 1 = yes, 0 = no. unsolcap 7 r 0h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no.
idt confidential 145 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo procwidget 6 r 0h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. formatovrd 4 r 0h n/a (hard-coded) stream format override: 1 = yes, 0 = no. ampparovrd 3 r 0h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 0h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 0h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 1h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). 7.8.1. portd (nid = 0dh): pincap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000ch field name bits r/w default reset rsvd2 31:17 r 0000h n/a (hard-coded) reserved. eapdcap 16 r 1h n/a (hard-coded) eapd support: 1 = yes, 0 = no. field name bits r/w default reset
idt confidential 146 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo vrefcntrl 15:8 r 00h n/a (hard-coded) vref support: bit 7 = reserved bit 6 = reserved bit 5 = 100% support (1 = yes, 0 = no) bit 4 = 80% support (1 = yes, 0 = no) bit 3 = reserved bit 2 = gnd support (1 = yes, 0 = no) bit 1 = 50% support (1 = yes, 0 = no) bit 0 = hi-z support (1 = yes, 0 = no) rsvd1 7 r 0h n/a (hard-coded) reserved. balancedio 6 r 1h n/a (hard-coded) balanced i/o support: 1 = yes, 0 = no. incap 5 r 0h n/a (hard-coded) input support: 1 = yes, 0 = no. outcap 4 r 1h n/a (hard-coded) output support: 1 = yes, 0 = no. hdphdrvcap 3 r 0h n/a (hard-coded) headphone amp present: 1 = yes, 0 = no. presdtctcap 2 r 0h n/a (hard-coded) presence detection support: 1 = yes, 0 = no. trigrqd 1 r 0h n/a (hard-coded) trigger required for impedance sense: 1 = yes, 0 = no. impsensecap 0 r 0h n/a (hard-coded) impedance sense support: 1 = yes, 0 = no. 7.8.2. portd (nid = 0dh): conlst reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000eh field name bits r/w default reset
idt confidential 147 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. lform 7 r 0h n/a (hard-coded) connection list format: 1 = long-form (15-bi t) nid entries, 0 = short-form (7-bit) nid entries. conl 6:0 r 03h n/a (hard-coded) number of nid entries in connection list. 7.8.3. portd (nid = 0dh): conlstentry0 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0200h field name bits r/w default reset conl3 31:24 r 00h n/a (hard-coded) reserved conl2 23:16 r 1ch n/a (hard-coded) mixeroutvol selector widget (0x1c) conl1 15:8 r 14h n/a (hard-coded) dac1 converter widget (0x14) conl0 7:0 r 13h n/a (hard-coded) dac0 converter widget (0x13) 7.8.4. portd (nid = 0dh): conselectctrl reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 701h get f0100h
idt confidential 148 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo field name bits r/w default reset rsvd 31:2 r 00000000h n/a (hard-coded) reserved. index 1:0 rw 0h por - dafg - ulr connection select control index. 7.8.5. portd (nid = 0dh): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved. settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. act 5:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved. set 1:0 rw 0h por - dafg - lr current power state setting for this widget.
idt confidential 149 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.8.6. portd (nid = 0dh): pinwcntrl reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 707h get f0700h field name bits r/w default reset rsvd2 31:7 r 000000h n/a (hard-coded) reserved. outen 6 rw 0h por - dafg - ulr output enable: 1 = enabled, 0 = disabled. rsvd1 5:0 r 0h n/a (hard-coded) reserved. 7.8.7. portd (nid = 0dh): eapdbtllr reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 70ch get f0c00h field name bits r/w default reset rsvd2 31:2 r 00000000h n/a (hard-coded) reserved. eapd 1 rw 1h por - dafg - ulr eapd control: 1 = set eapd pin to 1 (powered) up if this pin is powered up, 0 = set eapd pin to 0. rsvd1 0 r 0h n/a (hard-coded) reserved. 7.8.8. portd (nid = 0dh): configdefault reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 71fh 71eh 71dh 71ch
idt confidential 150 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo get f1f00h / f1e00h / f1d00h / f1c00h field name bits r/w default reset portconnectivity 31:30 rw 2h por port connectivity: 0h = port complex is connected to a jack 1h = no physical connection for port 2h = fixed function device is attached 3h = both jack and internal device attached (info in all other fields refers to in- tegrated device, any presence detection refers to jack) location 29:24 rw 10h por location bits [5..4]: 0h = external on primary chassis 1h = internal 2h = separate chassis 3h = other bits [3..0]: 0h = n/a 1h = rear 2h = front 3h = left 4h = right 5h = top 6h = bottom 7h-9h = special ah-fh = reserved 7.8.8. portd (nid = 0dh): configdefault reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0)
idt confidential 151 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo device 23:20 rw 1h por default device: 0h = line out 1h = speaker 2h = hp out 3h = cd 4h = spdif out 5h = digital other out 6h = modem line side 7h = modem handset side 8h = line in 9h = aux ah = mic in bh = telephony ch = spdif in dh = digital other in eh = reserved fh = other connectiontype 19:16 rw 7h por connection type: 0h = unknown 1h = 1/8" stereo/mono 2h = 1/4" stereo/mono 3h = atapi internal 4h = rca 5h = optical 6h = other digital 7h = other analog 8h = multichannel analog (din) 9h = xlr/professional ah = rj-11 (modem) bh = combination ch-eh = reserved fh = other field name bits r/w default reset
idt confidential 152 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo color 15:12 rw 0h por color: 0h = unknown 1h = black 2h = grey 3h = blue 4h = green 5h = red 6h = orange 7h = yellow 8h = purple 9h = pink ah-dh = reserved eh = white fh = other misc 11:8 rw 1h por miscellaneous: bits [3..1] = reserved bit 0 = jack detect override association 7:4 rw 1h por default assocation. sequence 3:0 rw 0h por sequence. field name bits r/w default reset
idt confidential 153 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.9. porte (nid = 0eh) : wcap (i2s output) reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. type 23:20 r 4h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined delay 19:16 r 0h n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 0h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no. dig 9 r 0h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). connlist 8 r 1h n/a (hard-coded) connection list present: 1 = yes, 0 = no. unsolcap 7 r 1h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no.
idt confidential 154 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo procwidget 6 r 0h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. formatovrd 4 r 0h n/a (hard-coded) stream format override: 1 = yes, 0 = no. ampparovrd 3 r 0h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 0h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 0h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 1h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). 7.9.1. porte (nid = 0eh): pincap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000ch field name bits r/w default reset rsvd2 31:17 r 0000h n/a (hard-coded) reserved. eapdcap 16 r 1h n/a (hard-coded) eapd support: 1 = yes, 0 = no. field name bits r/w default reset
idt confidential 155 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo vrefcntrl 15:8 r 00h n/a (hard-coded) vref support: bit 7 = reserved bit 6 = reserved bit 5 = 100% support (1 = yes, 0 = no) bit 4 = 80% support (1 = yes, 0 = no) bit 3 = reserved bit 2 = gnd support (1 = yes, 0 = no) bit 1 = 50% support (1 = yes, 0 = no) bit 0 = hi-z support (1 = yes, 0 = no) rsvd1 7 r 0h n/a (hard-coded) reserved. balancedio 6 r 0h n/a (hard-coded) balanced i/o support: 1 = yes, 0 = no. incap 5 r 0h n/a (hard-coded) input support: 1 = yes, 0 = no. outcap 4 r 1h n/a (hard-coded) output support: 1 = yes, 0 = no. hdphdrvcap 3 r 1h n/a (hard-coded) headphone amp present: 1 = yes, 0 = no. presdtctcap 2 r 1h n/a (hard-coded) presence detection support: 1 = yes, 0 = no. trigrqd 1 r 0h n/a (hard-coded) trigger required for impedance sense: 1 = yes, 0 = no. impsensecap 0 r 0h n/a (hard-coded) impedance sense support: 1 = yes, 0 = no. 7.9.2. porte (nid = 0eh): conlst reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000eh field name bits r/w default reset
idt confidential 156 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. lform 7 r 0h n/a (hard-coded) connection list format: 1 = long-form (15-bi t) nid entries, 0 = short-form (7-bit) nid entries. conl 6:0 r 03h n/a (hard-coded) number of nid entries in connection list. 7.9.3. porte (nid = 0eh): conlstentry0 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0200h field name bits r/w default reset conl3 31:24 r 00h n/a (hard-coded) dac2 converter widget (0x22) conl2 23:16 r 1ch n/a (hard-coded) mixeroutvol selector widget (0x1c) conl1 15:8 r 14h n/a (hard-coded) dac1 converter widget (0x14) conl0 7:0 r 13h n/a (hard-coded) dac0 converter widget (0x13) 7.9.4. porte (nid = 0eh): outampleft reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 780h get f8000h
idt confidential 157 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo field name bits r/w default reset rsvd1 31:8 r 00000000h n/a (hard-coded) reserved. mute 7 rw 0h por - dafg - ulr amp mute: 1 = muted, 0 = not muted gain 1:0 rw 0h por - dafg - ulr amp gain step number (see inampcap param eter pertaining to this widget). 7.9.5. porte (nid = 0eh): outampright reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 781h get f8100h field name bits r/w default reset rsvd1 31:8 r 00000000h n/a (hard-coded) reserved. mute 7 rw 0h por - dafg - ulr amp mute: 1 = muted, 0 = not muted gain 1:0 rw 0h por - dafg - ulr amp gain step number (see inampcap param eter pertaining to this widget). 7.9.6. porte (nid = 0eh): conselectctrl reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 701h get f0100h
idt confidential 158 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo field name bits r/w default reset rsvd 31:2 r 00000000h n/a (hard-coded) reserved. index 1:0 rw 0h por - dafg - ulr connection select control index. 7.9.7. porte (nid = 0eh): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved. settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. act 5:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved. set 1:0 rw 0h por - dafg - lr current power state setting for this widget.
idt confidential 159 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.9.8. porte (nid = 0eh): pinwcntrl reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 707h get f0700h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. hphnen 7 rw 0h por - dafg - ulr headphone amp enable: 1 = enabled, 0 = disabled. outen 6 rw 0h por - dafg - ulr output enable: 1 = enabled, 0 = disabled. inen 5 r 0h n/a (hard-coded) input enable: 1 = enabled, 0 = disabled. rsvd1 4:0 r 0h n/a (hard-coded) reserved. 7.9.9. porte (nid = 0eh): unsolresp reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 708h get f0800h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. en 7 rw 0h por - dafg - ulr unsolicited response enable (also enables wake events for this widget): 1 = enabled, 0 = disabled.
idt confidential 160 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo rsvd1 6 r 0h n/a (hard-coded) reserved. tag 5:0 rw 00h por - dafg - ulr software programmable field returned in top six bits (31:26) of every unsolicit- ed response generated by this node. 7.9.10. porte (nid = 0eh): chsense reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 709h get f0900h field name bits r/w default reset presdtct 31 r 0h por presence detection indicator: 1 = presence detected; 0 = presence not detect- ed. rsvd 30:0 r 00000000h n/a (hard-coded) reserved. 7.9.11. porte (nid = 0eh): eapdbtllr reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 70ch get f0c00h field name bits r/w default reset rsvd2 31:2 r 00000000h n/a (hard-coded) reserved. eapd 1 rw 1h por - dafg - ulr eapd control: 1 = set eapd pin to 1 (powered) up if this pin is powered up, 0 = set eapd pin to 0. field name bits r/w default reset
idt confidential 161 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo rsvd1 0 r 0h n/a (hard-coded) reserved. 7.9.12. porte (nid = 0eh): configdefault reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 71fh 71eh 71dh 71ch get f1f00h / f1e00h / f1d00h / f1c00h field name bits r/w default reset portconnectivity 31:30 rw 0h por port connectivity: 0h = port complex is connected to a jack 1h = no physical connection for port 2h = fixed function device is attached 3h = both jack and internal device attached (info in all other fields refers to in- tegrated device, any presence detection refers to jack) location 29:24 rw 01h por location bits [5..4]: 0h = external on primary chassis 1h = internal 2h = separate chassis 3h = other bits [3..0]: 0h = n/a 1h = rear 2h = front 3h = left 4h = right 5h = top 6h = bottom 7h-9h = special ah-fh = reserved field name bits r/w default reset
idt confidential 162 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo device 23:20 rw 0h por default device: 0h = line out 1h = speaker 2h = hp out 3h = cd 4h = spdif out 5h = digital other out 6h = modem line side 7h = modem handset side 8h = line in 9h = aux ah = mic in bh = telephony ch = spdif in dh = digital other in eh = reserved fh = other connectiontype 19:16 rw 1h por connection type: 0h = unknown 1h = 1/8" stereo/mono 2h = 1/4" stereo/mono 3h = atapi internal 4h = rca 5h = optical 6h = other digital 7h = other analog 8h = multichannel analog (din) 9h = xlr/professional ah = rj-11 (modem) bh = combination ch-eh = reserved fh = other field name bits r/w default reset
idt confidential 163 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo color 15:12 rw 4h por color: 0h = unknown 1h = black 2h = grey 3h = blue 4h = green 5h = red 6h = orange 7h = yellow 8h = purple 9h = pink ah-dh = reserved eh = white fh = other misc 11:8 rw 0h por miscellaneous: bits [3..1] = reserved bit 0 = jack detect override association 7:4 rw 5h por default assocation. sequence 3:0 rw 0h por sequence. field name bits r/w default reset
idt confidential 164 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.10. portf (nid = 0fh): wcap (i2s input) reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. type 23:20 r 4h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined delay 19:16 r 0h n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 0h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no. dig 9 r 0h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). connlist 8 r 1h n/a (hard-coded) connection list present: 1 = yes, 0 = no. unsolcap 7 r 1h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no.
idt confidential 165 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo procwidget 6 r 0h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. formatovrd 4 r 0h n/a (hard-coded) stream format override: 1 = yes, 0 = no. ampparovrd 3 r 0h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 0h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 1h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 1h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). 7.10.1. portf (nid = 0fh): pincap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000ch field name bits r/w default reset rsvd2 31:17 r 0000h n/a (hard-coded) reserved. eapdcap 16 r 1h n/a (hard-coded) eapd support: 1 = yes, 0 = no. field name bits r/w default reset
idt confidential 166 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo vrefcntrl 15:8 r 00h n/a (hard-coded) vref support: bit 7 = reserved bit 6 = reserved bit 5 = 100% support (1 = yes, 0 = no) bit 4 = 80% support (1 = yes, 0 = no) bit 3 = reserved bit 2 = gnd support (1 = yes, 0 = no) bit 1 = 50% support (1 = yes, 0 = no) bit 0 = hi-z support (1 = yes, 0 = no) rsvd1 7 r 0h n/a (hard-coded) reserved. balancedio 6 r 0h n/a (hard-coded) balanced i/o support: 1 = yes, 0 = no. incap 5 r 1h n/a (hard-coded) input support: 1 = yes, 0 = no. outcap 4 r 1h n/a (hard-coded) output support: 1 = yes, 0 = no. hdphdrvcap 3 r 0h n/a (hard-coded) headphone amp present: 1 = yes, 0 = no. presdtctcap 2 r 1h n/a (hard-coded) presence detection support: 1 = yes, 0 = no. trigrqd 1 r 0h n/a (hard-coded) trigger required for impedance sense: 1 = yes, 0 = no. impsensecap 0 r 0h n/a (hard-coded) impedance sense support: 1 = yes, 0 = no. 7.10.2. portf (nid = 0fh): conlst reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000eh field name bits r/w default reset
idt confidential 167 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. lform 7 r 0h n/a (hard-coded) connection list format: 1 = long-form (15-bi t) nid entries, 0 = short-form (7-bit) nid entries. conl 6:0 r 03h n/a (hard-coded) number of nid entries in connection list. 7.10.3. portf (nid = 0fh): conlstentry0 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0200h field name bits r/w default reset conl3 31:24 r 00h n/a (hard-coded) reserved conl2 23:16 r 00h n/a (hard-coded) reserved conl1 15:8 r 00h n/a (hard-coded) reserved conl0 7:0 r 00h n/a (hard-coded) reserved 7.10.4. portf (nid = 0fh): inampleft reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 360h get b2000h
idt confidential 168 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo field name bits r/w default reset rsvd1 31:2 r 00000000h n/a (hard-coded) reserved. gain 1:0 rw 0h por - dafg - ulr amp gain step number (see inampcap param eter pertaining to this widget). 7.10.5. portf (nid = 0fh): inampright reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 350h get b0000h field name bits r/w default reset rsvd1 31:2 r 00000000h n/a (hard-coded) reserved. gain 1:0 rw 0h por - dafg - ulr amp gain step number (see inampcap param eter pertaining to this widget). 7.10.6. portf (nid = 0fh): conselectctrl reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 701h get f0100h field name bits r/w default reset rsvd 31:2 r 00000000h n/a (hard-coded) reserved. index 1:0 rw 0h por - dafg - ulr connection select control index.
idt confidential 169 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.10.7. portf (nid = 0fh): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved. settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. act 5:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved. set 1:0 rw 0h por - dafg - lr current power state setting for this widget. 7.10.8. portf (nid = 0fh): pinwcntrl reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 707h get f0700h
idt confidential 170 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo field name bits r/w default reset rsvd2 31:7 r 000000h n/a (hard-coded) reserved. outen 6 rw 0h por - dafg - ulr output enable: 1 = enabled, 0 = disabled. inen 5 rw 0h por - dafg - ulr input enable: 1 = enabled, 0 = disabled. rsvd1 4:3 r 0h n/a (hard-coded) reserved. vrefen 2:0 rw 0h por - dafg - ulr vref selection (see vrefcntrl field of pincap parameter for supported selec- tions): 000b= hi-z 001b= 50% 010b= gnd 011b= reserved 100b= 80% 101b= 100% 110b= reserved 111b= reserved 7.10.9. portf (nid = 0fh): unsolresp reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 708h get f0800h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. en 7 rw 0h por - dafg - ulr unsolicited response enable (also enables wake events for this widget): 1 = enabled, 0 = disabled.
idt confidential 171 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo rsvd1 6 r 0h n/a (hard-coded) reserved. tag 5:0 rw 00h por - dafg - ulr software programmable field returned in top six bits (31:26) of every unsolicit- ed response generated by this node. 7.10.10. portf (nid = 0fh): chsense reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 709h get f0900h field name bits r/w default reset presdtct 31 r 0h por presence detection indicator: 1 = presence detected; 0 = presence not detect- ed. rsvd 30:0 r 00000000h n/a (hard-coded) reserved. 7.10.11. portf (nid = 0fh): eapdbtllr reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 70ch get f0c00h field name bits r/w default reset rsvd2 31:2 r 00000000h n/a (hard-coded) reserved. eapd 1 rw 1h por - dafg - ulr eapd control: 1 = set eapd pin to 1 (powered) up if this pin is powered up, 0 = set eapd pin to 0. field name bits r/w default reset
idt confidential 172 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo rsvd1 0 r 0h n/a (hard-coded) reserved. 7.10.12. portf (nid = 0fh): involleft reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 790h get f9000h field name bits r/w default reset rsvd1 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 0h por - dafg - ulr volume mute, 1=mute, 0 not muted gain 6:0 rw 00h por - dafg - ulr 0 to -95.25db in 0.75db steps.both headphone and btl output paths are ad- justed 7.10.13. portf (nid = 0fh): involright reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 791h get f9100h field name bits r/w default reset rsvd1 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 0h por - dafg - ulr volume mute, 1=mute, 0 not muted field name bits r/w default reset
idt confidential 173 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo gain 6:0 rw 00h por - dafg - ulr 0 to -95.25db in 0.75db steps.both headphone and btl output paths are ad- justed 7.10.14. portf (nid = 0fh): configdefault reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 71fh 71eh 71dh 71ch get f1f00h / f1e00h / f1d00h / f1c00h field name bits r/w default reset portconnectivity 31:30 rw 0h por port connectivity: 0h = port complex is connected to a jack 1h = no physical connection for port 2h = fixed function device is attached 3h = both jack and internal device attached (info in all other fields refers to in- tegrated device, any presence detection refers to jack) location 29:24 rw 01h por location bits [5..4]: 0h = external on primary chassis 1h = internal 2h = separate chassis 3h = other bits [3..0]: 0h = n/a 1h = rear 2h = front 3h = left 4h = right 5h = top 6h = bottom 7h-9h = special ah-fh = reserved field name bits r/w default reset
idt confidential 174 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo device 23:20 rw 8h por default device: 0h = line out 1h = speaker 2h = hp out 3h = cd 4h = spdif out 5h = digital other out 6h = modem line side 7h = modem handset side 8h = line in 9h = aux ah = mic in bh = telephony ch = spdif in dh = digital other in eh = reserved fh = other connectiontype 19:16 rw 1h por connection type: 0h = unknown 1h = 1/8" stereo/mono 2h = 1/4" stereo/mono 3h = atapi internal 4h = rca 5h = optical 6h = other digital 7h = other analog 8h = multichannel analog (din) 9h = xlr/professional ah = rj-11 (modem) bh = combination ch-eh = reserved fh = other field name bits r/w default reset
idt confidential 175 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo color 15:12 rw 3h por color: 0h = unknown 1h = black 2h = grey 3h = blue 4h = green 5h = red 6h = orange 7h = yellow 8h = purple 9h = pink ah-dh = reserved eh = white fh = other misc 11:8 rw 0h por miscellaneous: bits [3..1] = reserved bit 0 = jack detect override association 7:4 rw 2h por default assocation. sequence 3:0 rw eh por sequence. field name bits r/w default reset
idt confidential 176 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.11. monoout (nid = 10h): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. type 23:20 r 4h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined delay 19:16 r 0h n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 0h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no. dig 9 r 0h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). connlist 8 r 1h n/a (hard-coded) connection list present: 1 = yes, 0 = no. unsolcap 7 r 0h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no.
idt confidential 177 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo procwidget 6 r 0h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. formatovrd 4 r 0h n/a (hard-coded) stream format override: 1 = yes, 0 = no. ampparovrd 3 r 0h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 0h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 0h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 0h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). 7.11.1. monoout (nid = 10h): pincap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000ch field name bits r/w default reset rsvd2 31:17 r 0000h n/a (hard-coded) reserved. eapdcap 16 r 0h n/a (hard-coded) eapd support: 1 = yes, 0 = no. field name bits r/w default reset
idt confidential 178 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo vrefcntrl 15:8 r 00h n/a (hard-coded) vref support: bit 7 = reserved bit 6 = reserved bit 5 = 100% support (1 = yes, 0 = no) bit 4 = 80% support (1 = yes, 0 = no) bit 3 = reserved bit 2 = gnd support (1 = yes, 0 = no) bit 1 = 50% support (1 = yes, 0 = no) bit 0 = hi-z support (1 = yes, 0 = no) rsvd1 7 r 0h n/a (hard-coded) reserved. balancedio 6 r 0h n/a (hard-coded) balanced i/o support: 1 = yes, 0 = no. incap 5 r 0h n/a (hard-coded) input support: 1 = yes, 0 = no. outcap 4 r 1h n/a (hard-coded) output support: 1 = yes, 0 = no. hdphdrvcap 3 r 0h n/a (hard-coded) headphone amp present: 1 = yes, 0 = no. presdtctcap 2 r 0h n/a (hard-coded) presence detection support: 1 = yes, 0 = no. trigrqd 1 r 0h n/a (hard-coded) trigger required for impedance sense: 1 = yes, 0 = no. impsensecap 0 r 0h n/a (hard-coded) impedance sense support: 1 = yes, 0 = no. 7.11.2. monoout (nid = 10h): conlst reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000eh field name bits r/w default reset
idt confidential 179 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. lform 7 r 0h n/a (hard-coded) connection list format: 1 = long-form (15-bi t) nid entries, 0 = short-form (7-bit) nid entries. conl 6:0 r 01h n/a (hard-coded) number of nid entries in connection list. 7.11.3. monoout (nid = 10h): conlstentry0 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0200h field name bits r/w default reset conl3 31:24 r 00h n/a (hard-coded) unused list entry. conl2 23:16 r 00h n/a (hard-coded) unused list entry. conl1 15:8 r 00h n/a (hard-coded) unused list entry. conl0 7:0 r 1ah n/a (hard-coded) monomix summing widget (0x1a) 7.11.4. monoout (nid = 10h): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h
idt confidential 180 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved. settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. act 5:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved. set 1:0 rw 0h por - dafg - lr current power state setting for this widget. 7.11.5. monoout (nid = 10h): pinwcntrl reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 707h get f0700h field name bits r/w default reset rsvd2 31:7 r 000000h n/a (hard-coded) reserved. outen 6 rw 0h por - dafg - ulr output enable: 1 = enabled, 0 = disabled.
idt confidential 181 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo rsvd1 5:0 r 0h n/a (hard-coded) reserved. 7.11.6. monoout (nid = 10h): configdefault reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 71fh 71eh 71dh 71ch get f1f00h / f1e00h / f1d00h / f1c00h field name bits r/w default reset portconnectivity 31:30 rw 1h por port connectivity: 0h = port complex is connected to a jack 1h = no physical connection for port 2h = fixed function device is attached 3h = both jack and internal device attached (info in all other fields refers to in- tegrated device, any presence detection refers to jack) location 29:24 rw 00h por location bits [5..4]: 0h = external on primary chassis 1h = internal 2h = separate chassis 3h = other bits [3..0]: 0h = n/a 1h = rear 2h = front 3h = left 4h = right 5h = top 6h = bottom 7h-9h = special ah-fh = reserved field name bits r/w default reset
idt confidential 182 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo device 23:20 rw fh por default device: 0h = line out 1h = speaker 2h = hp out 3h = cd 4h = spdif out 5h = digital other out 6h = modem line side 7h = modem handset side 8h = line in 9h = aux ah = mic in bh = telephony ch = spdif in dh = digital other in eh = reserved fh = other connectiontype 19:16 rw 0h por connection type: 0h = unknown 1h = 1/8" stereo/mono 2h = 1/4" stereo/mono 3h = atapi internal 4h = rca 5h = optical 6h = other digital 7h = other analog 8h = multichannel analog (din) 9h = xlr/professional ah = rj-11 (modem) bh = combination ch-eh = reserved fh = other field name bits r/w default reset
idt confidential 183 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo color 15:12 rw 0h por color: 0h = unknown 1h = black 2h = grey 3h = blue 4h = green 5h = red 6h = orange 7h = yellow 8h = purple 9h = pink ah-dh = reserved eh = white fh = other misc 11:8 rw 0h por miscellaneous: bits [3..1] = reserved bit 0 = jack detect override association 7:4 rw fh por default assocation. sequence 3:0 rw 0h por sequence. field name bits r/w default reset
idt confidential 184 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.12. dmic0 (nid = 11h): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. type 23:20 r 4h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined delay 19:16 r 0h n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 0h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no. digitalstrm 9 r 0h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). connlist 8 r 0h n/a (hard-coded) connection list present: 1 = yes, 0 = no. unsolcap 7 r 1h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no.
idt confidential 185 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo procwidget 6 r 0h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. formatovrd 4 r 0h n/a (hard-coded) stream format override: 1 = yes, 0 = no. ampparovrd 3 r 0h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 0h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 1h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 1h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). 7.12.1. dmic0 (nid = 11h): pincap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000ch field name bits r/w default reset rsvd2 31:17 r 0000h n/a (hard-coded) reserved. eapdcap 16 r 0h n/a (hard-coded) eapd support: 1 = yes, 0 = no. field name bits r/w default reset
idt confidential 186 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo vrefcntrl 15:8 r 00h n/a (hard-coded) vref support: bit 7 = reserved bit 6 = reserved bit 5 = 100% support (1 = yes, 0 = no) bit 4 = 80% support (1 = yes, 0 = no) bit 3 = reserved bit 2 = gnd support (1 = yes, 0 = no) bit 1 = 50% support (1 = yes, 0 = no) bit 0 = hi-z support (1 = yes, 0 = no) rsvd1 7 r 0h n/a (hard-coded) reserved. balancedio 6 r 0h n/a (hard-coded) balanced i/o support: 1 = yes, 0 = no. incap 5 r 1h n/a (hard-coded) input support: 1 = yes, 0 = no. outcap 4 r 0h n/a (hard-coded) output support: 1 = yes, 0 = no. hphndrvcap 3 r 0h n/a (hard-coded) headphone amp present: 1 = yes, 0 = no. presdtctcap 2 r 1h n/a (hard-coded) presence detection support: 1 = yes, 0 = no. trigrqd 1 r 0h n/a (hard-coded) trigger required for impedance sense: 1 = yes, 0 = no. impsensecap 0 r 0h n/a (hard-coded) impedance sense support: 1 = yes, 0 = no. 7.12.2. dmic0 (nid = 11h): inampleft reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 360h get b2000h field name bits r/w default reset
idt confidential 187 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo field name bits r/w default reset rsvd1 31:2 r 00000000h n/a (hard-coded) reserved. gain 1:0 rw 0h por - dafg - ulr amp gain step number (see inampcap param eter pertaining to this widget). 7.12.3. dmic0 (nid = 11h): inampright reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 350h get b0000h field name bits r/w default reset rsvd1 31:2 r 00000000h n/a (hard-coded) reserved. gain 1:0 rw 0h por - dafg - ulr amp gain step number (see inampcap param eter pertaining to this widget). 7.12.4. dmic0 (nid = 11h): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved. settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget.
idt confidential 188 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. act 5:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved. set 1:0 rw 0h por - dafg - lr current power state setting for this widget. 7.12.5. dmic0 (nid = 11h): pinwcntrl reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 707h get f0700h field name bits r/w default reset rsvd2 31:6 r 0000000h n/a (hard-coded) reserved. inen 5 rw 0h por - dafg - ulr input enable: 1 = enabled, 0 = disabled. rsvd1 4:0 r 00h n/a (hard-coded) reserved. field name bits r/w default reset
idt confidential 189 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.12.6. dmic0 (nid = 11h): unsolresp reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 708h get f0800h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. en 7 rw 0h por - dafg - ulr unsolicited response enable (also enables wake events for this widget): 1 = enabled, 0 = disabled. rsvd1 6 r 0h n/a (hard-coded) reserved. tag 5:0 rw 00h por - dafg - ulr software programmable field returned in top six bits (31:26) of every unsolicit- ed response generated by this node. 7.12.7. dmic0 (nid = 11h): chsense reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 709h get f0900h field name bits r/w default reset presdtct 31 r 0h por presence detection indicator: 1 = presence detected; 0 = presence not detect- ed. rsvd 30:0 r 00000000h n/a (hard-coded) reserved.
idt confidential 190 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.12.8. dmic0 (nid = 11h): configdefault reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 71fh 71eh 71dh 71ch get f1f00h / f1e00h / f1d00h / f1c00h field name bits r/w default reset portconnectivity 31:30 rw 2h por port connectivity: 0h = port complex is connected to a jack 1h = no physical connection for port 2h = fixed function device is attached 3h = both jack and internal device attached (info in all other fields refers to in- tegrated device, any presence detection refers to jack) location 29:24 rw 10h por location bits [5..4]: 0h = external on primary chassis 1h = internal 2h = separate chassis 3h = other bits [3..0]: 0h = n/a 1h = rear 2h = front 3h = left 4h = right 5h = top 6h = bottom 7h-9h = special ah-fh = reserved
idt confidential 191 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo device 23:20 rw ah por default device: 0h = line out 1h = speaker 2h = hp out 3h = cd 4h = spdif out 5h = digital other out 6h = modem line side 7h = modem handset side 8h = line in 9h = aux ah = mic in bh = telephony ch = spdif in dh = digital other in eh = reserved fh = other connectiontype 19:16 rw 3h por connection type: 0h = unknown 1h = 1/8" stereo/mono 2h = 1/4" stereo/mono 3h = atapi internal 4h = rca 5h = optical 6h = other digital 7h = other analog 8h = multichannel analog (din) 9h = xlr/professional ah = rj-11 (modem) bh = combination ch-eh = reserved fh = other field name bits r/w default reset
idt confidential 192 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo color 15:12 rw 0h por color: 0h = unknown 1h = black 2h = grey 3h = blue 4h = green 5h = red 6h = orange 7h = yellow 8h = purple 9h = pink ah-dh = reserved eh = white fh = other misc 11:8 rw 1h por miscellaneous: bits [3..1] = reserved bit 0 = jack detect override association 7:4 rw 3h por default assocation. sequence 3:0 rw 0h por sequence. field name bits r/w default reset
idt confidential 193 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.13. dmic1vol (nid = 12h): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. type 23:20 r fh n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined delay 19:16 r 0h n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 0h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no. digitalstrm 9 r 0h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). connlist 8 r 1h n/a (hard-coded) connection list present: 1 = yes, 0 = no. unsolcap 7 r 0h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no.
idt confidential 194 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo procwidget 6 r 0h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. formatovrd 4 r 0h n/a (hard-coded) stream format override: 1 = yes, 0 = no. ampparovrd 3 r 0h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 0h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 1h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 1h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). 7.13.1. dmic1vol (nid = 12h): conlst reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000eh field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. lform 7 r 0h n/a (hard-coded) connection list format: 1 = long-form (15-bi t) nid entries, 0 = short-form (7-bit) nid entries. conl 6:0 r 01h n/a (hard-coded) number of nid entries in connection list. field name bits r/w default reset
idt confidential 195 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.13.2. dmic1vol (nid = 12h): conlstentry0 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0200h field name bits r/w default reset conl3 31:24 r 00h n/a (hard-coded) unused list entry. conl2 23:16 r 00h n/a (hard-coded) unused list entry. conl1 15:8 r 00h n/a (hard-coded) unused list entry. conl0 7:0 r 20h n/a (hard-coded) dig1pin pin widget (0x20) 7.13.3. dmic1vol (nid = 12h): inampleft reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 360h get b2000h field name bits r/w default reset rsvd1 31:2 r 00000000h n/a (hard-coded) reserved. gain 1:0 rw 0h por - dafg - ulr amp gain step number (see inampcap param eter pertaining to this widget). 7.13.4. dmic1vol (nid = 12h): inampright reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 350h get b0000h
idt confidential 196 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo field name bits r/w default reset rsvd1 31:2 r 00000000h n/a (hard-coded) reserved. gain 1:0 rw 0h por - dafg - ulr amp gain step number (see inampcap param eter pertaining to this widget). 7.13.5. dmic1vol (nid = 12h): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved. settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. act 5:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved. set 1:0 rw 0h por - dafg - lr current power state setting for this widget.
idt confidential 197 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.14. dac0 (nid = 13h): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. type 23:20 r 0h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined delay 19:16 r dh n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 1h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no. dig 9 r 0h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). connlist 8 r 0h n/a (hard-coded) connection list present: 1 = yes, 0 = no. unsolcap 7 r 0h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no.
idt confidential 198 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo procwidget 6 r 0h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. formatovrd 4 r 0h n/a (hard-coded) stream format override: 1 = yes, 0 = no. ampparovrd 3 r 0h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 1h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 0h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 1h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). 7.14.1. dac0 (nid = 13h): cnvtr reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 2h get a0000h field name bits r/w default reset rsvd2 31:16 r 0000h n/a (hard-coded) reserved. strmtype 15 r 0h n/a (hard-coded) stream type: 1 = non-pcm, 0 = pcm. frmtsmplrate 14 rw 0h por - dafg - ulr sample base rate: 1 = 44.1khz, 0 = 48khz. field name bits r/w default reset
idt confidential 199 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo smplratemultp 13:11 rw 0h por - dafg - ulr sample base rate multiple: 000b= x1 (48khz/44.1khz or less) 001b= x2 (96khz/88.2khz/32khz) 010b= x3 (144khz) 011b= x4 (192khz/176.4khz) 100b-111b reserved smplratediv 10:8 rw 0h por - dafg - ulr sample base rate divider: 000b= divide by 1 (48khz/44.1khz) 001b= divide by 2 (24khz/20.05khz) 010b= divide by 3 (16khz/32khz) 011b= divide by 4 (11.025khz) 100b= divide by 5 (9.6khz) 101b= divide by 6 (8khz) 110b= divide by 7 111b= divide by 8 (6khz) rsvd1 7 r 0h n/a (hard-coded) reserved. bitspersmpl 6:4 rw 3h por - dafg - ulr bits per sample: 000b= 8 bits 001b= 16 bits 010b= 20 bits 011b= 24 bits 100b= 32 bits 101b-111b= reserved nmbrchan 3:0 rw 1h por - dafg - ulr total number of channels in the stream assigned to this converter: 0000b-1111b= 1-16 channels. 7.14.2. dac0 (nid = 13h): outampleft reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 3a0h get ba000h field name bits r/w default reset
idt confidential 200 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. gain 6:0 rw 7fh por - dafg - ulr amp gain step number (see outampcap parameter pertaining to this widget). 7.14.3. dac0 (nid = 13h): outampright reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 390h get b8000h field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. gain 6:0 rw 7fh por - dafg - ulr amp gain step number (see outampcap parameter pertaining to this widget). 7.14.4. dac0 (nid = 13h): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved.
idt confidential 201 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. act 5:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved. set 1:0 rw 3h por - dafg - lr current power state setting for this widget. 7.14.5. dac0 (nid = 13h): cnvtrid reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 706h get f0600h field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. strm 7:4 rw 0h por - s&dafg - lr - ps stream id: 0h = converter "off", 1h-fh = valid id's. ch 3:0 rw 0h por - s&dafg - lr - ps channel assignment ("ch" and "ch+1" assi gned as a pair, for a stereo convert- er). field name bits r/w default reset
idt confidential 202 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.14.6. dac0 (nid = 13h): eapdbtllr reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 70ch get f0c00h field name bits r/w default reset rsvd2 31:3 r 00000000h n/a (hard-coded) reserved. swapen 2 rw 0h por - dafg - ulr swap enable: 1 = l/r swap enabled, 0 = l/r swap disabled. rsvd1 1:0 r 0h n/a (hard-coded) reserved. 7.15. dac1 (nid = 14h): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. type 23:20 r 0h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined
idt confidential 203 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo delay 19:16 r dh n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 1h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no. dig 9 r 0h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). connlist 8 r 0h n/a (hard-coded) connection list present: 1 = yes, 0 = no. unsolcap 7 r 0h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no. procwidget 6 r 0h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. formatovrd 4 r 0h n/a (hard-coded) stream format override: 1 = yes, 0 = no. ampparovrd 3 r 0h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 1h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 0h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 1h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). field name bits r/w default reset
idt confidential 204 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.15.1. dac1 (nid = 14h): cnvtr reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 2h get a0000h field name bits r/w default reset rsvd2 31:16 r 0000h n/a (hard-coded) reserved. strmtype 15 r 0h n/a (hard-coded) stream type: 1 = non-pcm, 0 = pcm. frmtsmplrate 14 rw 0h por - dafg - ulr sample base rate: 1 = 44.1khz, 0 = 48khz. smplratemultp 13:11 rw 0h por - dafg - ulr sample base rate multiple: 000b= x1 (48khz/44.1khz or less) 001b= x2 (96khz/88.2khz/32khz) 010b= x3 (144khz) 011b= x4 (192khz/176.4khz) 100b-111b reserved smplratediv 10:8 rw 0h por - dafg - ulr sample base rate divider: 000b= divide by 1 (48khz/44.1khz) 001b= divide by 2 (24khz/20.05khz) 010b= divide by 3 (16khz/32khz) 011b= divide by 4 (11.025khz) 100b= divide by 5 (9.6khz) 101b= divide by 6 (8khz) 110b= divide by 7 111b= divide by 8 (6khz) rsvd1 7 r 0h n/a (hard-coded) reserved.
idt confidential 205 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo bitspersmpl 6:4 rw 3h por - dafg - ulr bits per sample: 000b= 8 bits 001b= 16 bits 010b= 20 bits 011b= 24 bits 100b= 32 bits 101b-111b= reserved nmbrchan 3:0 rw 1h por - dafg - ulr total number of channels in the stream assigned to this converter: 0000b-1111b= 1-16 channels. 7.15.2. dac1 (nid = 14h): outampleft reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 3a0h get ba000h field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. gain 6:0 rw 7fh por - dafg - ulr amp gain step number (see outampcap parameter pertaining to this widget). 7.15.3. dac1 (nid = 14h): outampright reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 390h get b8000h field name bits r/w default reset
idt confidential 206 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. gain 6:0 rw 7fh por - dafg - ulr amp gain step number (see outampcap parameter pertaining to this widget). 7.15.4. dac1 (nid = 14h): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved. settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. act 5:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved.
idt confidential 207 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo set 1:0 rw 3h por - dafg - lr current power state setting for this widget. 7.15.5. dac1 (nid = 14h): cnvtrid reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 706h get f0600h field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. strm 7:4 rw 0h por - s&dafg - lr - ps stream id: 0h = converter "off", 1h-fh = valid id's. ch 3:0 rw 0h por - s&dafg - lr - ps channel assignment ("ch" and "ch+1" assi gned as a pair, for a stereo convert- er). 7.15.6. dac1 (nid = 14h): eapdbtllr reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 70ch get f0c00h field name bits r/w default reset rsvd2 31:3 r 00000000h n/a (hard-coded) reserved. swapen 2 rw 0h por - dafg - ulr swap enable: 1 = l/r swap enabled, 0 = l/r swap disabled. rsvd1 1:0 r 0h n/a (hard-coded) reserved. field name bits r/w default reset
idt confidential 208 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.16. adc0 (nid = 15h): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. type 23:20 r 1h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined delay 19:16 r dh n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 0h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no. dig 9 r 0h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). connlist 8 r 1h n/a (hard-coded) connection list present: 1 = yes, 0 = no. unsolcap 7 r 0h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no.
idt confidential 209 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo procwidget 6 r 1h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. formatovrd 4 r 0h n/a (hard-coded) stream format override: 1 = yes, 0 = no. ampparovrd 3 r 0h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 0h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 0h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 1h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). 7.16.1. adc0 (nid = 15h): conlst reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000eh field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. lform 7 r 0h n/a (hard-coded) connection list format: 1 = long-form (15-bi t) nid entries, 0 = short-form (7-bit) nid entries. conl 6:0 r 01h n/a (hard-coded) number of nid entries in connection list. field name bits r/w default reset
idt confidential 210 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.16.2. adc0 (nid = 15h): conlstentry0 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0200h field name bits r/w default reset conl3 31:24 r 00h n/a (hard-coded) unused list entry. conl2 23:16 r 00h n/a (hard-coded) unused list entry. conl1 15:8 r 00h n/a (hard-coded) unused list entry. conl0 7:0 r 20h n/a (hard-coded) adc0mux selector widget (0x17) 7.16.3. adc0 (nid = 15h): cnvtr reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 2h get a0000h field name bits r/w default reset rsvd2 31:16 r 0000h n/a (hard-coded) reserved. strmtype 15 r 0h n/a (hard-coded) stream type: 1 = non-pcm, 0 = pcm. frmtsmplrate 14 rw 0h por - dafg - ulr sample base rate: 1 = 44.1khz, 0 = 48khz.
idt confidential 211 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo smplratemultp 13:11 rw 0h por - dafg - ulr sample base rate multiple: 000b= x1 (48khz/44.1khz or less) 001b= x2 (96khz/88.2khz/32khz) 010b= x3 (144khz) 011b= x4 (192khz/176.4khz) 100b-111b reserved smplratediv 10:8 rw 0h por - dafg - ulr sample base rate divider: 000b= divide by 1 (48khz/44.1khz) 001b= divide by 2 (24khz/20.05khz) 010b= divide by 3 (16khz/32khz) 011b= divide by 4 (11.025khz) 100b= divide by 5 (9.6khz) 101b= divide by 6 (8khz) 110b= divide by 7 111b= divide by 8 (6khz) rsvd1 7 r 0h n/a (hard-coded) reserved. bitspersmpl 6:4 rw 3h por - dafg - ulr bits per sample: 000b= 8 bits 001b= 16 bits 010b= 20 bits 011b= 24 bits 100b= 32 bits 101b-111b= reserved nmbrchan 3:0 rw 1h por - dafg - ulr total number of channels in the stream assigned to this converter: 0000b-1111b= 1-16 channels. 7.16.4. adc0 (nid = 15h): procstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 703h get f0300h field name bits r/w default reset
idt confidential 212 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. hpfocdis 7 rw 0h por - dafg - ulr hpf offset calculation disable. 1 = calculation disabled; 0 = calculation en- abled. rsvd1 6:2 r 00h n/a (hard-coded) reserved. adchpfbyp 1:0 rw 1h por - dafg - ulr processing state: 00b= bypass the adc hpf ("off"), 01b-11b= adc hpf is en- abled ("on" or "benign"). 7.16.5. adc0 (nid = 15h): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved. settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved.
idt confidential 213 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo act 5:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved. set 1:0 rw 3h por - dafg - lr current power state setting for this widget. 7.16.6. adc0 (nid = 15h): cnvtrid reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 706h get f0600h field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. strm 7:4 rw 0h por - s&dafg - lr - ps stream id: 0h = converter "off", 1h-fh = valid id's. ch 3:0 rw 0h por - s&dafg - lr - ps channel assignment ("ch" and "ch+1" assi gned as a pair, for a stereo convert- er). 7.17. adc1 (nid = 1bh): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset
idt confidential 214 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. type 23:20 r 1h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined delay 19:16 r dh n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 0h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no. dig 9 r 0h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). connlist 8 r 1h n/a (hard-coded) connection list present: 1 = yes, 0 = no. unsolcap 7 r 0h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no. procwidget 6 r 1h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no.
idt confidential 215 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo formatovrd 4 r 0h n/a (hard-coded) stream format override: 1 = yes, 0 = no. ampparovrd 3 r 0h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 0h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 0h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 1h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). 7.17.1. adc1 (nid = 1bh): conlst reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000eh field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. lform 7 r 0h n/a (hard-coded) connection list format: 1 = long-form (15-bi t) nid entries, 0 = short-form (7-bit) nid entries. conl 6:0 r 01h n/a (hard-coded) number of nid entries in connection list. 7.17.2. adc1 (nid = 1bh): conlstentry0 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0200h field name bits r/w default reset
idt confidential 216 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo field name bits r/w default reset conl3 31:24 r 00h n/a (hard-coded) unused list entry. conl2 23:16 r 00h n/a (hard-coded) unused list entry. conl1 15:8 r 00h n/a (hard-coded) unused list entry. conl0 7:0 r 18h n/a (hard-coded) adc1mux widget (0x18) 7.17.3. adc1 (nid = 1bh): cnvtr reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 2h get a0000h field name bits r/w default reset rsvd2 31:16 r 0000h n/a (hard-coded) reserved. strmtype 15 r 0h n/a (hard-coded) stream type: 1 = non-pcm, 0 = pcm. frmtsmplrate 14 rw 0h por - dafg - ulr sample base rate: 1 = 44.1khz, 0 = 48khz. smplratemultp 13:11 rw 0h por - dafg - ulr sample base rate multiple: 000b= x1 (48khz/44.1khz or less) 001b= x2 (96khz/88.2khz/32khz) 010b= x3 (144khz) 011b= x4 (192khz/176.4khz) 100b-111b reserved
idt confidential 217 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo smplratediv 10:8 rw 0h por - dafg - ulr sample base rate divider: 000b= divide by 1 (48khz/44.1khz) 001b= divide by 2 (24khz/20.05khz) 010b= divide by 3 (16khz/32khz) 011b= divide by 4 (11.025khz) 100b= divide by 5 (9.6khz) 101b= divide by 6 (8khz) 110b= divide by 7 111b= divide by 8 (6khz) rsvd1 7 r 0h n/a (hard-coded) reserved. bitspersmpl 6:4 rw 3h por - dafg - ulr bits per sample: 000b= 8 bits 001b= 16 bits 010b= 20 bits 011b= 24 bits 100b= 32 bits 101b-111b= reserved nmbrchan 3:0 rw 1h por - dafg - ulr total number of channels in the stream assigned to this converter: 0000b-1111b= 1-16 channels. 7.17.4. adc1 (nid = 1bh): procstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 703h get f0300h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. hpfocdis 7 rw 0h por - dafg - ulr hpf offset calculation disable. 1 = calculation disabled; 0 = calculation en- abled. field name bits r/w default reset
idt confidential 218 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo rsvd1 6:2 r 00h n/a (hard-coded) reserved. adchpfbyp 1:0 rw 1h por - dafg - ulr processing state: 00b= bypass the adc hpf ("off"), 01b-11b= adc hpf is en- abled ("on" or "benign"). 7.17.5. adc1 (nid = 1bh): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved. settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. act 5:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved. set 1:0 rw 3h por - dafg - lr current power state setting for this widget. field name bits r/w default reset
idt confidential 219 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.17.6. adc1 (nid = 1bh): cnvtrid reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 706h get f0600h field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. strm 7:4 rw 0h por - s&dafg - lr - ps stream id: 0h = converter "off", 1h-fh = valid id's. ch 3:0 rw 0h por - s&dafg - lr - ps channel assignment ("ch" and "ch+1" assi gned as a pair, for a stereo convert- er).
idt confidential 220 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.18. adc0mux (nid = 17h): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. type 23:20 r 3h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined delay 19:16 r 0h n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 1h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no. digitalstrm 9 r 0h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). connlist 8 r 1h n/a (hard-coded) connection list present: 1 = yes, 0 = no. unsolcap 7 r 0h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no.
idt confidential 221 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo procwidget 6 r 0h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. formatovrd 4 r 0h n/a (hard-coded) stream format override: 1 = yes, 0 = no. ampparamovrd 3 r 1h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 1h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 0h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 1h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). 7.18.1. adc0mux (nid = 17h): conlst reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000eh field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. lform 7 r 0h n/a (hard-coded) connection list format: 1 = long-form (15-bi t) nid entries, 0 = short-form (7-bit) nid entries. conl 6:0 r 05?h n/a (hard-coded) number of nid entries in connection list. field name bits r/w default reset
idt confidential 222 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.18.2. adc0mux (nid = 17h): conlstentry4 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0204h field name bits r/w default reset conl7 31:24 r 00h n/a (hard-coded) unused list entry. conl6 23:16 r 00h n/a (hard-coded) reserved conl5 15:8 r 00h n/a (hard-coded) reserved conl4 7:0 r 12h n/a (hard-coded) dmic1 widget (0x12) 7.18.3. adc0mux (nid = 17h): conlstentry0 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0200h field name bits r/w default reset conl3 31:24 r 11h n/a (hard-coded) dmic0 widget (0x11) conl2 23:16 r 0fh n/a (hard-coded) port f pin widget (0x0f) conl1 15:8 r 0ah n/a (hard-coded) port a pin widget (0x0a) conl0 7:0 r 1bh n/a (hard-coded) mixer summing widget (0x1b)
idt confidential 223 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.18.4. adc0mux (nid = 17h): outampcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0012h field name bits r/w default reset mute 31 r 1h n/a (hard-coded) mute support: 1 = yes, 0 = no. rsvd3 30:23 r 00h n/a (hard-coded) reserved. stepsize 22:16 r 03h n/a (hard-coded) size of each step in the gain range: 0 to 127 = .25db to 32db, in .25db steps. rsvd2 15 r 0h n/a (hard-coded) reserved. numsteps 14:8 r 2eh n/a (hard-coded) number of gains steps (number of possible settings - 1). rsvd1 7 r 0h n/a (hard-coded) reserved. offset 6:0 r 10h n/a (hard-coded) indicates which step is 0db 7.18.5. adc0mux (nid = 17h): outampleft reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 3a0h get ba000h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved.
idt confidential 224 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. rsvd1 6 r 0h n/a (hard-coded) reserved. gain 5:0 rw 10h por - dafg - ulr amp gain step number (see outampcap parameter pertaining to this widget). 7.18.6. adc0mux (nid = 17h): outampright reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 390h get b8000h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. rsvd1 6 r 0h n/a (hard-coded) reserved. gain 5:0 rw 10h por - dafg - ulr amp gain step number (see outampcap parameter pertaining to this widget). 7.18.7. adc0mux (nid = 17h): conselectctrl reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 701h get f0100h field name bits r/w default reset
idt confidential 225 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo field name bits r/w default reset rsvd 31:3 r 00000000h n/a (hard-coded) reserved. index 2:0 rw 0h por - dafg - ulr connection select control index. 7.18.8. adc0mux (nid = 17h): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved. settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. act 5:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved. set 1:0 rw 0h por - dafg - lr current power state setting for this widget.
idt confidential 226 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.18.9. adc0mux (nid = 17h): eapdbtllr reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 70ch get f0c00h field name bits r/w default reset rsvd2 31:3 r 00000000h n/a (hard-coded) reserved. swapen 2 rw 0h por - dafg - ulr swap enable: 1 = l/r swap enabled, 0 = l/r swap disabled. rsvd1 1:0 r 0h n/a (hard-coded) reserved. 7.19. adc1mux (nid = 18h): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. type 23:20 r 3h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined
idt confidential 227 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo delay 19:16 r 0h n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 1h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no. digitalstrm 9 r 0h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). connlist 8 r 1h n/a (hard-coded) connection list present: 1 = yes, 0 = no. unsolcap 7 r 0h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no. procwidget 6 r 0h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. formatovrd 4 r 0h n/a (hard-coded) stream format override: 1 = yes, 0 = no. ampparamovrd 3 r 1h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 1h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 0h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 1h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). field name bits r/w default reset
idt confidential 228 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.19.1. adc1mux (nid = 18h): conlst reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000eh field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. lform 7 r 0h n/a (hard-coded) connection list format: 1 = long-form (15-bi t) nid entries, 0 = short-form (7-bit) nid entries. conl 6:0 r 05h n/a (hard-coded) number of nid entries in connection list. 7.19.2. adc1mux (nid = 18h): conlstentry4 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0204h field name bits r/w default reset conl7 31:24 r 00h n/a (hard-coded) unused list entry. conl6 23:16 r 00h n/a (hard-coded) reserved. conl5 15:8 r 00h n/a (hard-coded) reserved conl4 7:0 r 12h n/a (hard-coded) dmic1 widget (0x12)
idt confidential 229 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.19.3. adc1mux (nid = 18h): conlstentry0 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0200h field name bits r/w default reset conl3 31:24 r 11h n/a (hard-coded) dmic0 widget (0x11) conl2 23:16 r 0fh n/a (hard-coded) port f pin widget (0x0f) conl1 15:8 r 0ah n/a (hard-coded) port a pin widget (0x0a) conl0 7:0 r 1bh n/a (hard-coded) mixer summing widget (0x1b) 7.19.4. adc1mux (nid = 18h): outampcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0012h field name bits r/w default reset mute 31 r 1h n/a (hard-coded) mute support: 1 = yes, 0 = no. rsvd3 30:23 r 00h n/a (hard-coded) reserved. stepsize 22:16 r 03h n/a (hard-coded) size of each step in the gain range: 0 to 127 = .25db to 32db, in .25db steps. rsvd2 15 r 0h n/a (hard-coded) reserved.
idt confidential 230 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo numsteps 14:8 r 2eh n/a (hard-coded) number of gains steps (number of possible settings - 1). rsvd1 7 r 0h n/a (hard-coded) reserved. offset 6:0 r 10h n/a (hard-coded) indicates which step is 0db 7.19.5. adc1mux (nid = 18h): outampleft reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 3a0h get ba000h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. rsvd1 6 r 0h n/a (hard-coded) reserved. gain 5:0 rw 10h por - dafg - ulr amp gain step number (see outampcap parameter pertaining to this widget). 7.19.6. adc1mux (nid = 18h): outampright reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 390h get b8000h field name bits r/w default reset
idt confidential 231 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. rsvd1 6 r 0h n/a (hard-coded) reserved. gain 5:0 rw 10h por - dafg - ulr amp gain step number (see outampcap parameter pertaining to this widget). 7.19.7. adc1mux (nid = 18h): conselectctrl reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 701h get f0100h field name bits r/w default reset rsvd 31:3 r 00000000h n/a (hard-coded) reserved. index 2:0 rw 0h por - dafg - ulr connection select control index. 7.19.8. adc1mux (nid = 18h): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved.
idt confidential 232 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. act 5:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved. set 1:0 rw 0h por - dafg - lr current power state setting for this widget. 7.19.9. adc1mux (nid = 18h): eapdbtllr reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 70ch get f0c00h field name bits r/w default reset rsvd2 31:3 r 00000000h n/a (hard-coded) reserved. swapen 2 rw 0h por - dafg - ulr swap enable: 1 = l/r swap enabled, 0 = l/r swap disabled. rsvd1 1:0 r 0h n/a (hard-coded) reserved. field name bits r/w default reset
idt confidential 233 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.20. monomux (nid = 19h): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. type 23:20 r 3h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined delay 19:16 r 0h n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 0h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no. dig 9 r 0h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). connlist 8 r 1h n/a (hard-coded) connection list present: 1 = yes, 0 = no. unsolcap 7 r 0h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no.
idt confidential 234 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo procwidget 6 r 0h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. formatovrd 4 r 0h n/a (hard-coded) stream format override: 1 = yes, 0 = no. ampparovrd 3 r 0h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 0h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 0h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 1h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). 7.20.1. monomux (nid = 19h): conlst reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000eh field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. lform 7 r 0h n/a (hard-coded) connection list format: 1 = long-form (15-bi t) nid entries, 0 = short-form (7-bit) nid entries. conl 6:0 r 03h n/a (hard-coded) number of nid entries in connection list. field name bits r/w default reset
idt confidential 235 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.20.2. monomux (nid = 19h): conlstentry0 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0200h field name bits r/w default reset conl3 31:24 r 00h n/a (hard-coded) dac2 converter widget (0x22) conl2 23:16 r 1ch n/a (hard-coded) mixeroutvol selector widget (0x1c) conl1 15:8 r 14h n/a (hard-coded) dac1 converter widget (0x14) conl0 7:0 r 13h n/a (hard-coded) dac0 converter widget (0x13) 7.20.3. monomux (nid = 19h): conselectctrl reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 701h get f0100h field name bits r/w default reset rsvd 31:2 r 0000000h n/a (hard-coded) reserved. index 1:0 rw 0h por - dafg - ulr connection select control index. 7.20.4. monomux (nid = 19h): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h
idt confidential 236 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved. settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. act 5:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved. set 1:0 rw 0h por - dafg - lr current power state setting for this widget. 7.21. monomix (nid = 1ah): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved.
idt confidential 237 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo type 23:20 r 2h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined delay 19:16 r 0h n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 0h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no. dig 9 r 0h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). connlist 8 r 1h n/a (hard-coded) connection list present: 1 = yes, 0 = no. unsolcap 7 r 0h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no. procwidget 6 r 0h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. formatovrd 4 r 0h n/a (hard-coded) stream format override: 1 = yes, 0 = no. field name bits r/w default reset
idt confidential 238 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo ampparovrd 3 r 0h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 0h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 0h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 0h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). 7.21.1. monomix (nid = 1ah): conlst reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000eh field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. lform 7 r 0h n/a (hard-coded) connection list format: 1 = long-form (15-bi t) nid entries, 0 = short-form (7-bit) nid entries. conl 6:0 r 01h n/a (hard-coded) number of nid entries in connection list. 7.21.2. monomix (nid = 1ah): conlstentry0 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0200h field name bits r/w default reset
idt confidential 239 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo field name bits r/w default reset conl3 31:24 r 00h n/a (hard-coded) unused list entry. conl2 23:16 r 00h n/a (hard-coded) unused list entry. conl1 15:8 r 00h n/a (hard-coded) unused list entry. conl0 7:0 r 19h n/a (hard-coded) monomux selector widget (0x19) 7.21.3. monomix (nid = 1ah): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved. settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. act 5:4 r 3h por - dafg - lr actual power state of this widget.
idt confidential 240 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo rsvd1 3:2 r 0h n/a (hard-coded) reserved. set 1:0 rw 0h por - dafg - lr current power state setting for this widget. field name bits r/w default reset
idt confidential 241 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.22. mixer (nid = 1bh): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. type 23:20 r 2h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined delay 19:16 r 0h n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 0h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no. dig 9 r 0h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). connlist 8 r 1h n/a (hard-coded) connection list present: 1 = yes, 0 = no. unsolcap 7 r 0h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no.
idt confidential 242 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo procwidget 6 r 0h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. formatovrd 4 r 0h n/a (hard-coded) stream format override: 1 = yes, 0 = no. ampparovrd 3 r 1h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 0h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 1h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 1h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). 7.22.1. mixer (nid = 1bh): inampcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000dh field name bits r/w default reset mute 31 r 1h n/a (hard-coded) mute support: 1 = yes, 0 = no. rsvd3 30:23 r 00h n/a (hard-coded) reserved. stepsize 22:16 r 05h n/a (hard-coded) size of each step in the gain range: 0 to 127 = .25db to 32db, in .25db steps. field name bits r/w default reset
idt confidential 243 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo rsvd2 15 r 0h n/a (hard-coded) reserved. numsteps 14:8 r 1fh n/a (hard-coded) number of gains steps (number of possible settings - 1). rsvd1 7 r 0h n/a (hard-coded) reserved. offset 6:0 r 17h n/a (hard-coded) indicates which step is 0db 7.22.2. mixer (nid = 1bh): conlst reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000eh field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. lform 7 r 0h n/a (hard-coded) connection list format: 1 = long-form (15-bi t) nid entries, 0 = short-form (7-bit) nid entries. conl 6:0 r 04h n/a (hard-coded) number of nid entries in connection list. 7.22.3. mixer (nid = 1bh): conlstentry4 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0204h field name bits r/w default reset
idt confidential 244 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo field name bits r/w default reset conl7 31:24 r 00h n/a (hard-coded) unused list entry. conl6 23:16 r 00h n/a (hard-coded) unused list entry. conl5 15:8 r 00h n/a (hard-coded) reserved. conl4 7:0 r 00h n/a (hard-coded) reserved. 7.22.4. mixer (nid = 1bh): conlstentry0 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0200h field name bits r/w default reset conl3 31:24 r 0fh n/a (hard-coded) port f pin widget (0x0f). uses inampleft3/inampright3 controls. conl2 23:16 r 0ah n/a (hard-coded) port a pin widget (0x0a). uses inampleft2/inampright2 controls. conl1 15:8 r 14h n/a (hard-coded) dac1 widget (0x14). uses inampleft1/inampright1 controls. conl0 7:0 r 13h n/a (hard-coded) dac0 widget (0x13). uses inampleft0/inampright0 controls. 7.22.5. mixer (nid = 1bh): inampleft0 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 360h get b2000h
idt confidential 245 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. rsvd1 6:5 r 0h n/a (hard-coded) reserved. gain 4:0 rw 17h por - dafg - ulr amp gain step number (see inampcap param eter pertaining to this widget). 7.22.6. mixer (nid = 1bh): inampright0 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 350h get b0000h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. rsvd1 6:5 r 0h n/a (hard-coded) reserved. gain 4:0 rw 17h por - dafg - ulr amp gain step number (see inampcap param eter pertaining to this widget). 7.22.7. mixer (nid = 1bh): inampleft1 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 361h get b2001h
idt confidential 246 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. rsvd1 6:5 r 0h n/a (hard-coded) reserved. gain 4:0 rw 17h por - dafg - ulr amp gain step number (see inampcap param eter pertaining to this widget). 7.22.8. mixer (nid = 1bh): inampright1 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 351h get b0001h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. rsvd1 6:5 r 0h n/a (hard-coded) reserved. gain 4:0 rw 17h por - dafg - ulr amp gain step number (see inampcap param eter pertaining to this widget). 7.22.9. mixer (nid = 1bh): inampleft2 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 362h get b2002h
idt confidential 247 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. rsvd1 6:5 r 0h n/a (hard-coded) reserved. gain 4:0 rw 17h por - dafg - ulr amp gain step number (see inampcap param eter pertaining to this widget). 7.22.10. mixer (nid = 1bh): inampright2 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 352h get b0002h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. rsvd1 6:5 r 0h n/a (hard-coded) reserved. gain 4:0 rw 17h por - dafg - ulr amp gain step number (see inampcap param eter pertaining to this widget). 7.22.11. mixer (nid = 1bh): inampleft3 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 363h get b2003h
idt confidential 248 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. rsvd1 6:5 r 0h n/a (hard-coded) reserved. gain 4:0 rw 17h por - dafg - ulr amp gain step number (see inampcap param eter pertaining to this widget). 7.22.12. mixer (nid = 1bh): inampright3 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 353h get b0003h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. rsvd1 6:5 r 0h n/a (hard-coded) reserved. gain 4:0 rw 17h por - dafg - ulr amp gain step number (see inampcap param eter pertaining to this widget). 7.22.13. mixer (nid = 1bh): inampleft4 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 364h get b2004h
idt confidential 249 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. rsvd1 6:5 r 0h n/a (hard-coded) reserved. gain 4:0 rw 17h por - dafg - ulr amp gain step number (see inampcap param eter pertaining to this widget). 7.22.14. mixer (nid = 1bh): inampright4 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 354h get b0004h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. rsvd1 6:5 r 0h n/a (hard-coded) reserved. gain 4:0 rw 17h por - dafg - ulr amp gain step number (see inampcap param eter pertaining to this widget). 7.22.15. mixer (nid = 1bh): inampleft5 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 365h get b2005h
idt confidential 250 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. rsvd1 6:5 r 0h n/a (hard-coded) reserved. gain 4:0 rw 17h por - dafg - ulr amp gain step number (see inampcap param eter pertaining to this widget). 7.22.16. mixer (nid = 1bh): inampright5 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 355h get b0005h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. rsvd1 6:5 r 0h n/a (hard-coded) reserved. gain 4:0 rw 17h por - dafg - ulr amp gain step number (see inampcap param eter pertaining to this widget). 7.22.17. mixer (nid = 1bh): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h
idt confidential 251 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved. settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. act 5:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved. set 1:0 rw 0h por - dafg - lr current power state setting for this widget. 7.23. mixeroutvol (nid = 1ch): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved.
idt confidential 252 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo type 23:20 r 3h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined delay 19:16 r 0h n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 0h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no. dig 9 r 0h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). connlist 8 r 1h n/a (hard-coded) connection list present: 1 = yes, 0 = no. unsolcap 7 r 0h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no. procwidget 6 r 0h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. formatovrd 4 r 0h n/a (hard-coded) stream format override: 1 = yes, 0 = no. field name bits r/w default reset
idt confidential 253 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo ampparovrd 3 r 1h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 1h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 0h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 1h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). 7.23.1. mixeroutvol (nid = 1ch): conlst reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000eh field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. lform 7 r 0h n/a (hard-coded) connection list format: 1 = long-form (15-bi t) nid entries, 0 = short-form (7-bit) nid entries. conl 6:0 r 01h n/a (hard-coded) number of nid entries in connection list. 7.23.2. mixeroutvol (nid = 1ch): conlstentry0 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0200h field name bits r/w default reset
idt confidential 254 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo field name bits r/w default reset conl3 31:24 r 00h n/a (hard-coded) unused list entry. conl2 23:16 r 00h n/a (hard-coded) unused list entry. conl1 15:8 r 00h n/a (hard-coded) unused list entry. conl0 7:0 r 1bh n/a (hard-coded) mixer summing widget (0x1b) 7.23.3. mixeroutvol (nid = 1ch): outampcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0012h field name bits r/w default reset mute 31 r 1h n/a (hard-coded) mute support: 1 = yes, 0 = no. rsvd3 30:23 r 00h n/a (hard-coded) reserved. stepsize 22:16 r 05h n/a (hard-coded) size of each step in the gain range: 0 to 127 = .25db to 32db, in .25db steps. rsvd2 15 r 0h n/a (hard-coded) reserved. numsteps 14:8 r 1fh n/a (hard-coded) number of gains steps (number of possible settings - 1). rsvd1 7 r 0h n/a (hard-coded) reserved.
idt confidential 255 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo offset 6:0 r 1fh n/a (hard-coded) indicates which step is 0db 7.23.4. mixeroutvol (nid = 1ch): outampleft reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 3a0h get ba000h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. rsvd1 6:5 r 0h n/a (hard-coded) reserved. gain 4:0 rw 1fh por - dafg - ulr amp gain step number (see outampcap parameter pertaining to this widget). 7.23.5. mixeroutvol (nid = 1ch): outampright reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 390h get b8000h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. field name bits r/w default reset
idt confidential 256 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo rsvd1 6:5 r 0h n/a (hard-coded) reserved. gain 4:0 rw 1fh por - dafg - ulr amp gain step number (see outampcap parameter pertaining to this widget). 7.23.6. mixeroutvol (nid = 1ch): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved. settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. act 5:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved. set 1:0 rw 0h por - dafg - lr current power state setting for this widget. field name bits r/w default reset
idt confidential 257 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.24. spdifout0 (nid = 1dh): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. type 23:20 r 0h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined delay 19:16 r 4h n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 0h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no. dig 9 r 1h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). connlist 8 r 0h n/a (hard-coded) connection list present: 1 = yes, 0 = no. unsolcap 7 r 0h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no.
idt confidential 258 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo procwidget 6 r 0h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. formatovrd 4 r 1h n/a (hard-coded) stream format override: 1 = yes, 0 = no. ampparovrd 3 r 1h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 1h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 0h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 1h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). 7.24.1. spdifout0 (nid = 1dh): pcmcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000ah field name bits r/w default reset rsvd2 31:21 r 000h n/a (hard-coded) reserved. b32 20 r 0h n/a (hard-coded) 32 bit audio format support: 1 = yes, 0 = no. b24 19 r 1h n/a (hard-coded) 24 bit audio format support: 1 = yes, 0 = no. field name bits r/w default reset
idt confidential 259 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo b20 18 r 1h n/a (hard-coded) 20 bit audio format support: 1 = yes, 0 = no. b16 17 r 1h n/a (hard-coded) 16 bit audio format support: 1 = yes, 0 = no. b8 16 r 0h n/a (hard-coded) 8 bit audio format support: 1 = yes, 0 = no. rsvd1 15:12 r 0h n/a (hard-coded) reserved. r12 11 r 0h n/a (hard-coded) 384khz rate support: 1 = yes, 0 = no. r11 10 r 1h n/a (hard-coded) 192khz rate support: 1 = yes, 0 = no. r10 9 r 0h n/a (hard-coded) 176.4khz rate support: 1 = yes, 0 = no. r9 8 r 1h n/a (hard-coded) 96khz rate support: 1 = yes, 0 = no. r8 7 r 1h n/a (hard-coded) 88.2khz rate support: 1 = yes, 0 = no. r7 6 r 1h n/a (hard-coded) 48khz rate support: 1 = yes, 0 = no. r6 5 r 1h n/a (hard-coded) 44.1khz rate support: 1 = yes, 0 = no. r5 4 r 0h n/a (hard-coded) 32khz rate support: 1 = yes, 0 = no. r4 3 r 0h n/a (hard-coded) 22.05khz rate support: 1 = yes, 0 = no. r3 2 r 0h n/a (hard-coded) 16khz rate support: 1 = yes, 0 = no. field name bits r/w default reset
idt confidential 260 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo r2 1 r 0h n/a (hard-coded) 11.025khz rate support: 1 = yes, 0 = no. r1 0 r 0h n/a (hard-coded) 8khz rate support: 1 = yes, 0 = no. 7.24.2. spdifout0 (nid = 1dh): streamcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000bh field name bits r/w default reset rsvd 31:3 r 00000000h n/a (hard-coded) reserved. ac3 2 r 1h n/a (hard-coded) ac-3 formatted data support: 1 = yes, 0 = no. float32 1 r 0h n/a (hard-coded) float32 formatted data support: 1 = yes, 0 = no. pcm 0 r 1h n/a (hard-coded) pcm-formatted data support: 1 = yes, 0 = no. 7.24.3. spdifout0 (nid = 1dh): outampcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0012h field name bits r/w default reset mute 31 r 1h n/a (hard-coded) mute support: 1 = yes, 0 = no. field name bits r/w default reset
idt confidential 261 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo rsvd3 30:23 r 00h n/a (hard-coded) reserved. stepsize 22:16 r 00h n/a (hard-coded) size of each step in the gain range: 0 to 127 = .25db to 32db, in .25db steps. rsvd2 15 r 0h n/a (hard-coded) reserved. numsteps 14:8 r 00h n/a (hard-coded) number of gains steps (number of possible settings - 1). rsvd1 7 r 0h n/a (hard-coded) reserved. offset 6:0 r 00h n/a (hard-coded) indicates which step is 0db 7.24.4. spdifout0 (nid = 1dh): cnvtr reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 2h get a0000h field name bits r/w default reset rsvd2 31:16 r 0000h n/a (hard-coded) reserved. frmtnonpcm 15 rw 0h por - dafg - ulr stream type: 1 = non-pcm, 0 = pcm. frmtsmplrate 14 rw 0h por - dafg - ulr sample base rate: 1 = 44.1khz, 0 = 48khz. field name bits r/w default reset
idt confidential 262 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo smplratemultp 13:11 rw 0h por - dafg - ulr sample base rate multiple: 000b= x1 (48khz/44.1khz or less) 001b= x2 (96khz/88.2khz/32khz) 010b= x3 (144khz) 011b= x4 (192khz/176.4khz) 100b-111b reserved smplratediv 10:8 rw 0h por - dafg - ulr sample base rate divider: 000b= divide by 1 (48khz/44.1khz) 001b= divide by 2 (24khz/20.05khz) 010b= divide by 3 (16khz/32khz) 011b= divide by 4 (11.025khz) 100b= divide by 5 (9.6khz) 101b= divide by 6 (8khz) 110b= divide by 7 111b= divide by 8 (6khz) rsvd1 7 r 0h n/a (hard-coded) reserved. bitspersmpl 6:4 rw 3h por - dafg - ulr bits per sample: 000b= 8 bits 001b= 16 bits 010b= 20 bits 011b= 24 bits 100b= 32 bits 101b-111b= reserved nmbrchan 3:0 rw 1h por - dafg - ulr total number of channels in the stream assigned to this converter: 0000b-1111b= 1-16 channels. 7.24.5. spdifout0 (nid = 1dh): outampleft reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 3a0h get ba000h field name bits r/w default reset
idt confidential 263 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 0h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. rsvd1 6:0 r 00h n/a (hard-coded) reserved. 7.24.6. spdifout0 (nid = 1dh): outampright reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 390h get b8000h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 0h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. rsvd1 6:0 r 00h n/a (hard-coded) reserved. 7.24.7. spdifout0 (nid = 1dh): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved.
idt confidential 264 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. act 5:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved. set 1:0 rw 3h por - dafg - lr current power state setting for this widget. 7.24.8. spdifout0 (nid = 1dh): cnvtrid reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 706h get f0600h field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. strm 7:4 rw 0h por - s&dafg - lr - ps stream id: 0h = converter "off", 1h-fh = valid id's. ch 3:0 rw 0h por - s&dafg - lr - ps channel assignment ("ch" and "ch+1" assi gned as a pair, for a stereo convert- er). field name bits r/w default reset
idt confidential 265 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.24.9. spdifout0 (nid = 1dh): digcnvtr reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 73fh 73eh 70eh 70dh get f0e00h / f0d00h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. keepalive 23 rw 0h por - dafg - ulr keep alive enable: 1 = clocking information maintained during d3, 0 = clock information not required during d3. rsvd1 22:15 r 00h n/a (hard-coded) reserved. cc 14:8 rw 00h por - dafg - ulr cc: category code. l 7 rw 0h por - dafg - ulr l: generation level. pro 6 rw 0h por - dafg - ulr pro: professional. audio 5 rw 0h por - dafg - ulr /audio: non-audio. copy 4 rw 0h por - dafg - ulr copy: copyright. pre 3 rw 0h por - dafg - ulr pre: preemphasis. vcfg 2 rw 0h por - dafg - ulr vcfg: validity config. v 1 rw 0h por - dafg - ulr v: validity.
idt confidential 266 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo digen 0 rw 0h por - dafg - ulr digital enable: 1 = converter enabled, 0 = converter disable. 7.25. spdifout1 (nid = 1eh): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. type 23:20 r 0h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined delay 19:16 r 4h n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 0h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no. dig 9 r 1h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). field name bits r/w default reset
idt confidential 267 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo connlist 8 r 0h n/a (hard-coded) connection list present: 1 = yes, 0 = no. unsolcap 7 r 0h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no. procwidget 6 r 0h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. formatovrd 4 r 1h n/a (hard-coded) stream format override: 1 = yes, 0 = no. ampparovrd 3 r 1h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 1h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 0h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 1h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). 7.25.1. spdifout1 (nid = 1eh): pcmcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000ah field name bits r/w default reset rsvd2 31:21 r 000h n/a (hard-coded) reserved. field name bits r/w default reset
idt confidential 268 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo b32 20 r 0h n/a (hard-coded) 32 bit audio format support: 1 = yes, 0 = no. b24 19 r 1h n/a (hard-coded) 24 bit audio format support: 1 = yes, 0 = no. b20 18 r 1h n/a (hard-coded) 20 bit audio format support: 1 = yes, 0 = no. b16 17 r 1h n/a (hard-coded) 16 bit audio format support: 1 = yes, 0 = no. b8 16 r 0h n/a (hard-coded) 8 bit audio format support: 1 = yes, 0 = no. rsvd1 15:12 r 0h n/a (hard-coded) reserved. r12 11 r 0h n/a (hard-coded) 384khz rate support: 1 = yes, 0 = no. r11 10 r 1h n/a (hard-coded) 192khz rate support: 1 = yes, 0 = no. r10 9 r 0h n/a (hard-coded) 176.4khz rate support: 1 = yes, 0 = no. r9 8 r 1h n/a (hard-coded) 96khz rate support: 1 = yes, 0 = no. r8 7 r 1h n/a (hard-coded) 88.2khz rate support: 1 = yes, 0 = no. r7 6 r 1h n/a (hard-coded) 48khz rate support: 1 = yes, 0 = no. r6 5 r 1h n/a (hard-coded) 44.1khz rate support: 1 = yes, 0 = no. r5 4 r 0h n/a (hard-coded) 32khz rate support: 1 = yes, 0 = no. field name bits r/w default reset
idt confidential 269 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo r4 3 r 0h n/a (hard-coded) 22.05khz rate support: 1 = yes, 0 = no. r3 2 r 0h n/a (hard-coded) 16khz rate support: 1 = yes, 0 = no. r2 1 r 0h n/a (hard-coded) 11.025khz rate support: 1 = yes, 0 = no. r1 0 r 0h n/a (hard-coded) 8khz rate support: 1 = yes, 0 = no. 7.25.2. spdifout1 (nid = 1eh): streamcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000bh field name bits r/w default reset rsvd 31:3 r 00000000h n/a (hard-coded) reserved. ac3 2 r 1h n/a (hard-coded) ac-3 formatted data support: 1 = yes, 0 = no. float32 1 r 0h n/a (hard-coded) float32 formatted data support: 1 = yes, 0 = no. pcm 0 r 1h n/a (hard-coded) pcm-formatted data support: 1 = yes, 0 = no. 7.25.3. spdifout1 (nid = 1eh): outampcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0012h field name bits r/w default reset
idt confidential 270 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo field name bits r/w default reset mute 31 r 1h n/a (hard-coded) mute support: 1 = yes, 0 = no. rsvd3 30:23 r 00h n/a (hard-coded) reserved. stepsize 22:16 r 00h n/a (hard-coded) size of each step in the gain range: 0 to 127 = .25db to 32db, in .25db steps. rsvd2 15 r 0h n/a (hard-coded) reserved. numsteps 14:8 r 00h n/a (hard-coded) number of gains steps (number of possible settings - 1). rsvd1 7 r 0h n/a (hard-coded) reserved. offset 6:0 r 00h n/a (hard-coded) indicates which step is 0db 7.25.4. spdifout1 (nid = 1eh): cnvtr reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 2h get a0000h field name bits r/w default reset rsvd2 31:16 r 0000h n/a (hard-coded) reserved. frmtnonpcm 15 rw 0h por - dafg - ulr stream type: 1 = non-pcm, 0 = pcm. frmtsmplrate 14 rw 0h por - dafg - ulr sample base rate: 1 = 44.1khz, 0 = 48khz.
idt confidential 271 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo smplratemultp 13:11 rw 0h por - dafg - ulr sample base rate multiple: 000b= x1 (48khz/44.1khz or less) 001b= x2 (96khz/88.2khz/32khz) 010b= x3 (144khz) 011b= x4 (192khz/176.4khz) 100b-111b reserved smplratediv 10:8 rw 0h por - dafg - ulr sample base rate divider: 000b= divide by 1 (48khz/44.1khz) 001b= divide by 2 (24khz/20.05khz) 010b= divide by 3 (16khz/32khz) 011b= divide by 4 (11.025khz) 100b= divide by 5 (9.6khz) 101b= divide by 6 (8khz) 110b= divide by 7 111b= divide by 8 (6khz) rsvd1 7 r 0h n/a (hard-coded) reserved. bitspersmpl 6:4 rw 3h por - dafg - ulr bits per sample: 000b= 8 bits 001b= 16 bits 010b= 20 bits 011b= 24 bits 100b= 32 bits 101b-111b= reserved nmbrchan 3:0 rw 1h por - dafg - ulr total number of channels in the stream assigned to this converter: 0000b-1111b= 1-16 channels. 7.25.5. spdifout1 (nid = 1eh): outampleft reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 3a0h get ba000h field name bits r/w default reset
idt confidential 272 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 0h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. rsvd1 6:0 r 00h n/a (hard-coded) reserved. 7.25.6. spdifout1 (nid = 1eh): outampright reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 390h get b8000h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 0h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. rsvd1 6:0 r 00h n/a (hard-coded) reserved. 7.25.7. spdifout1 (nid = 1eh): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved.
idt confidential 273 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. act 5:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved. set 1:0 rw 3h por - dafg - lr current power state setting for this widget. 7.25.8. spdifout1 (nid = 1eh): cnvtrid reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 706h get f0600h field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. strm 7:4 rw 0h por - s&dafg - lr - ps stream id: 0h = converter "off", 1h-fh = valid id's. ch 3:0 rw 0h por - s&dafg - lr - ps channel assignment ("ch" and "ch+1" assi gned as a pair, for a stereo convert- er). field name bits r/w default reset
idt confidential 274 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.25.9. spdifout1 (nid = 1eh): digcnvtr reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 73fh 73eh 70eh 70dh get f0e00h / f0d00h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. keepalive 23 rw 0h por - dafg - ulr keep alive enable: 1 = clocking information maintained during d3, 0 = clock information not required during d3. rsvd1 22:15 r 00h n/a (hard-coded) reserved. cc 14:8 rw 00h por - dafg - ulr cc: category code. l 7 rw 0h por - dafg - ulr l: generation level. pro 6 rw 0h por - dafg - ulr pro: professional. audio 5 rw 0h por - dafg - ulr /audio: non-audio. copy 4 rw 0h por - dafg - ulr copy: copyright. pre 3 rw 0h por - dafg - ulr pre: preemphasis. vcfg 2 rw 0h por - dafg - ulr vcfg: validity config. v 1 rw 0h por - dafg - ulr v: validity.
idt confidential 275 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo digen 0 rw 0h por - dafg - ulr digital enable: 1 = converter enabled, 0 = converter disable. 7.26. dig0pin (nid = 1fh): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. type 23:20 r 4h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined delay 19:16 r 0h n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 0h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no. dig 9 r 1h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). field name bits r/w default reset
idt confidential 276 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo connlist 8 r 1h n/a (hard-coded) connection list present: 1 = yes, 0 = no. unsolcap 7 r 1h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no. procwidget 6 r 0h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. formatovrd 4 r 0h n/a (hard-coded) stream format override: 1 = yes, 0 = no. ampparovrd 3 r 0h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 0h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 0h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 1h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). 7.26.1. dig0pin (nid = 1fh): pincap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000ch field name bits r/w default reset rsvd2 31:17 r 0000h n/a (hard-coded) reserved. field name bits r/w default reset
idt confidential 277 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo eapdcap 16 r 0h n/a (hard-coded) eapd support: 1 = yes, 0 = no. vrefcntrl 15:8 r 00h n/a (hard-coded) vref support: bit 7 = reserved bit 6 = reserved bit 5 = 100% support (1 = yes, 0 = no) bit 4 = 80% support (1 = yes, 0 = no) bit 3 = reserved bit 2 = gnd support (1 = yes, 0 = no) bit 1 = 50% support (1 = yes, 0 = no) bit 0 = hi-z support (1 = yes, 0 = no) rsvd1 7 r 0h n/a (hard-coded) reserved. balancedio 6 r 0h n/a (hard-coded) balanced i/o support: 1 = yes, 0 = no. incap 5 r 0h n/a (hard-coded) input support: 1 = yes, 0 = no. outcap 4 r 1h n/a (hard-coded) output support: 1 = yes, 0 = no. hdphdrvcap 3 r 0h n/a (hard-coded) headphone amp present: 1 = yes, 0 = no. presdtctcap 2 r 1h n/a (hard-coded) presence detection support: 1 = yes, 0 = no. trigrqd 1 r 0h n/a (hard-coded) trigger required for impedance sense: 1 = yes, 0 = no. impsensecap 0 r 0h n/a (hard-coded) impedance sense support: 1 = yes, 0 = no. 7.26.2. dig0pin (nid = 1fh): conlst reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000eh field name bits r/w default reset
idt confidential 278 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. lform 7 r 0h n/a (hard-coded) connection list format: 1 = long-form (15-bi t) nid entries, 0 = short-form (7-bit) nid entries. conl 6:0 r 01h n/a (hard-coded) number of nid entries in connection list. 7.26.3. dig0pin (nid = 1fh): conlstentry0 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0200h field name bits r/w default reset conl3 31:24 r 00h n/a (hard-coded) unused list entry. conl2 23:16 r 00h n/a (hard-coded) unused list entry. conl1 15:8 r 00h n/a (hard-coded) unused list entry. conl0 7:0 r 1dh n/a (hard-coded) spdifout0 converter widget (0x1d) 7.26.4. dig0pin (nid = 1fh): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h
idt confidential 279 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved. settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. act 5:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved. set 1:0 rw 0h por - dafg - lr current power state setting for this widget. 7.26.5. dig0pin (nid = 1fh): pinwcntrl reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 707h get f0700h field name bits r/w default reset rsvd2 31:7 r 0000000h n/a (hard-coded) reserved. outen 6 rw 0h por - dafg - ulr output enable: 1 = enabled, 0 = disabled.
idt confidential 280 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo rsvd1 5:0 r 00h n/a (hard-coded) reserved. 7.26.6. dig0pin (nid = 1fh): unsolresp reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 708h get f0800h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. en 7 rw 0h por - dafg - ulr unsolicited response enable (also enables wake events for this widget): 1 = enabled, 0 = disabled. rsvd1 6 r 0h n/a (hard-coded) reserved. tag 5:0 rw 00h por - dafg - ulr software programmable field returned in top six bits (31:26) of every unsolicit- ed response generated by this node. 7.26.7. dig0pin (nid = 1fh): chsense reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 709h get f0900h field name bits r/w default reset presdtct 31 r 0h por presence detection indicator: 1 = presence detected; 0 = presence not detect- ed. field name bits r/w default reset
idt confidential 281 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo rsvd 30:0 r 00000000h n/a (hard-coded) reserved. 7.26.8. dig0pin (nid = 1fh): configdefault reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 71fh 71eh 71dh 71ch get f1f00h / f1e00h / f1d00h / f1c00h field name bits r/w default reset portconnectivity 31:30 rw 0h por port connectivity: 0h = port complex is connected to a jack 1h = no physical connection for port 2h = fixed function device is attached 3h = both jack and internal device attached (info in all other fields refers to in- tegrated device, any presence detection refers to jack) location 29:24 rw 1h por location bits [5..4]: 0h = external on primary chassis 1h = internal 2h = separate chassis 3h = other bits [3..0]: 0h = n/a 1h = rear 2h = front 3h = left 4h = right 5h = top 6h = bottom 7h-9h = special ah-fh = reserved field name bits r/w default reset
idt confidential 282 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo device 23:20 rw 4h por default device: 0h = line out 1h = speaker 2h = hp out 3h = cd 4h = spdif out 5h = digital other out 6h = modem line side 7h = modem handset side 8h = line in 9h = aux ah = mic in bh = telephony ch = spdif in dh = digital other in eh = reserved fh = other connectiontype 19:16 rw 5h por connection type: 0h = unknown 1h = 1/8" stereo/mono 2h = 1/4" stereo/mono 3h = atapi internal 4h = rca 5h = optical 6h = other digital 7h = other analog 8h = multichannel analog (din) 9h = xlr/professional ah = rj-11 (modem) bh = combination ch-eh = reserved fh = other field name bits r/w default reset
idt confidential 283 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo color 15:12 rw 1h por color: 0h = unknown 1h = black 2h = grey 3h = blue 4h = green 5h = red 6h = orange 7h = yellow 8h = purple 9h = pink ah-dh = reserved eh = white fh = other misc 11:8 rw 1h por miscellaneous: bits [3..1] = reserved bit 0 = jack detect override association 7:4 rw 6h por default assocation. sequence 3:0 rw 0h por sequence. 7.27. dig1pin (nid = 20h): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. field name bits r/w default reset
idt confidential 284 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo type 23:20 r 4h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined delay 19:16 r 0h n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 0h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no. dig 9 r 1h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). connlist 8 r 1h n/a (hard-coded) connection list present: 1 = yes, 0 = no. unsolcap 7 r 1h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no. procwidget 6 r 0h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. formatovrd 4 r 0h n/a (hard-coded) stream format override: 1 = yes, 0 = no. field name bits r/w default reset
idt confidential 285 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo ampparovrd 3 r 0h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 0h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 0h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 1h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). 7.27.1. dig1pin (nid = 20h): pincap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000ch field name bits r/w default reset rsvd2 31:17 r 0000h n/a (hard-coded) reserved. eapdcap 16 r 0h n/a (hard-coded) eapd support: 1 = yes, 0 = no. vrefcntrl 15:8 r 00h n/a (hard-coded) vref support: bit 7 = reserved bit 6 = reserved bit 5 = 100% support (1 = yes, 0 = no) bit 4 = 80% support (1 = yes, 0 = no) bit 3 = reserved bit 2 = gnd support (1 = yes, 0 = no) bit 1 = 50% support (1 = yes, 0 = no) bit 0 = hi-z support (1 = yes, 0 = no) rsvd1 7 r 0h n/a (hard-coded) reserved. field name bits r/w default reset
idt confidential 286 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo balancedio 6 r 0h n/a (hard-coded) balanced i/o support: 1 = yes, 0 = no. incap 5 r 1h n/a (hard-coded) input support: 1 = yes, 0 = no. outcap 4 r 1h n/a (hard-coded) output support: 1 = yes, 0 = no. hdphdrvcap 3 r 0h n/a (hard-coded) headphone amp present: 1 = yes, 0 = no. presdtctcap 2 r 1h n/a (hard-coded) presence detection support: 1 = yes, 0 = no. trigrqd 1 r 0h n/a (hard-coded) trigger required for impedance sense: 1 = yes, 0 = no. impsensecap 0 r 0h n/a (hard-coded) impedance sense support: 1 = yes, 0 = no. 7.27.2. dig1pin (nid = 20h): conlst reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000eh field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. lform 7 r 0h n/a (hard-coded) connection list format: 1 = long-form (15-bi t) nid entries, 0 = short-form (7-bit) nid entries. conl 6:0 r 01h n/a (hard-coded) number of nid entries in connection list. field name bits r/w default reset
idt confidential 287 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.27.3. dig1pin (nid = 20h): conlstentry0 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0200h field name bits r/w default reset conl3 31:24 r 00h n/a (hard-coded) unused list entry. conl2 23:16 r 00h n/a (hard-coded) unused list entry. conl1 15:8 r 00h n/a (hard-coded) unused list entry. conl0 7:0 r 1eh n/a (hard-coded) spdifout1 converter widget (0x1e) 7.27.4. dig1pin (nid = 20h): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved. settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. rsvd3 9 r 0h n/a (hard-coded) reserved.
idt confidential 288 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. act 5:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved. set 1:0 rw 0h por - dafg - lr current power state setting for this widget. 7.27.5. dig1pin (nid = 20h): pinwcntrl reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 707h get f0700h field name bits r/w default reset rsvd2 31:7 r 0000000h n/a (hard-coded) reserved. outen 6 rw 0h por - dafg - ulr output enable: 1 = enabled, 0 = disabled. inen 5 rw 0h por - dafg - ulr input enable: 1 = enabled, 0 = disabled. rsvd1 4:0 r 00h n/a (hard-coded) reserved. field name bits r/w default reset
idt confidential 289 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.27.6. dig1pin (nid = 20h): configdefault reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 71fh 71eh 71dh 71ch get f1f00h / f1e00h / f1d00h / f1c00h field name bits r/w default reset portconnectivity 31:30 rw 2h por port connectivity: 0h = port complex is connected to a jack 1h = no physical connection for port 2h = fixed function device is attached 3h = both jack and internal device attached (info in all other fields refers to in- tegrated device, any presence detection refers to jack) location 29:24 rw 18h por location bits [5..4]: 0h = external on primary chassis 1h = internal 2h = separate chassis 3h = other bits [3..0]: 0h = n/a 1h = rear 2h = front 3h = left 4h = right 5h = top 6h = bottom 7h-9h = special ah-fh = reserved
idt confidential 290 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo device 23:20 rw 5h por default device: 0h = line out 1h = speaker 2h = hp out 3h = cd 4h = spdif out 5h = digital other out 6h = modem line side 7h = modem handset side 8h = line in 9h = aux ah = mic in bh = telephony ch = spdif in dh = digital other in eh = reserved fh = other connectiontype 19:16 rw 6h por connection type: 0h = unknown 1h = 1/8" stereo/mono 2h = 1/4" stereo/mono 3h = atapi internal 4h = rca 5h = optical 6h = other digital 7h = other analog 8h = multichannel analog (din) 9h = xlr/professional ah = rj-11 (modem) bh = combination ch-eh = reserved fh = other field name bits r/w default reset
idt confidential 291 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo color 15:12 rw 0h por color: 0h = unknown 1h = black 2h = grey 3h = blue 4h = green 5h = red 6h = orange 7h = yellow 8h = purple 9h = pink ah-dh = reserved eh = white fh = other misc 11:8 rw 1h por miscellaneous: bits [3..1] = reserved bit 0 = jack detect override association 7:4 rw 7h por default assocation. sequence 3:0 rw 0h por sequence. field name bits r/w default reset
idt confidential 292 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.28. digbeep (nid = 21h): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd4 31:24 r 00h n/a (hard-coded) reserved. type 23:20 r 7h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined rsvd3 19:11 r 0h n/a (hard-coded) reserved. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no." rsvd2 9:4 r 0h n/a (hard-coded) reserved ampparovrd 3 r 1h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 1h n/a (hard-coded) output amp present: 1 = yes, 0 = no. rsvd1 1:0 r 0h n/a (hard-coded) reserved.
idt confidential 293 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.28.1. digbeep (nid = 21h): outampcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0012h field name bits r/w default reset mute 31 r 1h n/a (hard-coded) mute support: 1 = yes, 0 = no. rsvd3 30:23 r 00h n/a (hard-coded) reserved. stepsize 22:16 r 17h n/a (hard-coded) size of each step in the gain range: 0 to 127 = .25db to 32db, in .25db steps. rsvd2 15 r 0h n/a (hard-coded) reserved. numsteps 14:8 r 03h n/a (hard-coded) number of gains steps (number of possible settings - 1). rsvd1 7 r 0h n/a (hard-coded) reserved. offset 6:0 r 03h n/a (hard-coded) indicates which step is 0db 7.28.2. digbeep (nid = 21h): outampleft reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 3a0h get ba000h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved.
idt confidential 294 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo mute 7 rw 0h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. rsvd1 6:2 r 00h n/a (hard-coded) reserved. gain 1:0 rw 1h por - dafg - ulr amp gain step number (see outampcap parameter pertaining to this widget). 7.28.3. digbeep (nid = 21h): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved. settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. act 5:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved. field name bits r/w default reset
idt confidential 295 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo set 1:0 rw 0h por - dafg - lr current power state setting for this widget. 7.28.4. digbeep (nid = 21h): gen reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 70ah get f0a00h field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. divider 7:0 rw 00h por - dafg - lr enable internal pc-beep generation. divi der == 00h disables internal pc beep generation and enables normal operation of the codec. divider != 00h gener- ates the beep tone on all pin complexes that are currently configured as out- puts. the hd audio spec states that the beep tone frequency = (48khz hd audio sync rate) / (4*divider), producing tones from 47 hz to 12 khz (logarith- mic scale). 7.28.5. digbeep (nid = 21h): gain reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 77ah get f7a00h field name bits r/w default reset rsvd 31:3 r 000000h n/a (hard-coded) reserved. divider 2:0 rw 05h por - dafg - lr digital pc beep gain adjust in digital side 0h = -9db, 1h = -6db, 2h = -3db, 3h = 0db, 4h = +3db, 5h = +6db field name bits r/w default reset
idt confidential 296 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 7.29. i2c (nid = 22h): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. type 23:20 r fh n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined delay 19:16 r 0h n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 0h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 0h n/a (hard-coded) power state support: 1 = yes, 0 = no. dig 9 r 0h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). connlist 8 r 0h n/a (hard-coded) connection list present: 1 = yes, 0 = no.
idt confidential 297 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo unsolcap 7 r 0h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no. procwidget 6 r 0h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. formatovrd 4 r 0h n/a (hard-coded) stream format override: 1 = yes, 0 = no. ampparovrd 3 r 0h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 0h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 0h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 1h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). 7.29.1. i2c (nid = 22h): cntrl0 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 770h:&7afh get f7700h: 7af0h field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. field name bits r/w default reset
idt confidential 298 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo value 7:0 rw 0h por - dafg - ulr contrl register value of i2c module field name bits r/w default reset
idt confidential 299 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 8. pinout and packaging figure 26. 48qfn pin assignment 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 qfn dvdd_core** dmic_clk/gpio 1 dmic_0/gpio 2 sdata_out bitclk dvss** sdata_in dvdd* sync reset# i2s_secondary cap+ cap- v- mono_out avss1 avdd1 i2s_mclk i2s_sclk i2c_clk i2c_dat i2s_dout i2s_lrclk portd_+r portd_-r portd_-l portd_+l dmic1/gpio 0/spdifout1/aux_in vreg(+2.5v) avdd2 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 dvdd_io eapd spdif out0/gpio3/aux_out pvdd pvss pvdd avss2 portb_r portb_l avss2 porta_r porta_l vrefout_a i2s_din sense_a sense_b vreffilt cap2
idt confidential 300 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 8.0.1. 48qfn pin table pin name pin function i/o internal pull-up/pull-down 48 pin location dvdd_core 1.5v digital core regulator filter cap o(digital) none 1 dmic_clk/gpio1 digital mic clock outp ut/gpio1 i/o(digital) 60k pull-down 2 dvdd_io reference voltage (1.5v or 3.3v) i(digital) none 3 dmic0/gpio2 digital mic 01 input/ gpio2 i/o(digital) 60k pull-down 4 sdata_out hd audio serial data output from controller i/o(digital) none 5 bitclk hd audio bit clock i(digital) none 6 dvss digital ground i(digital) none 7 sdata_in hd audio serial data input to controller o(digital) none 8 dvdd digital vdd= 3.3v i(digital) none 9 sync hd audio frame sync i(digital) none 10 reset# hd audio reset i(digital) none 11 i2s_secondary secondary audio input i(digital) 60k pull-down 12 sense_a jack insertion de tection ports a,b, spdifout0 i(analog) none 13 sense_b jack insertion de tection ports e,f, dmic0, spdifout1 (dmic1) i(analog) none 14 i2s_mclk master clock for i2s po rt i/o(digital) 60k pull-down 15 i2s_sclk shift clock for i2s po rt i/o(digital) 60k pull-down 16 i2s_dout data output for i2s port (port e) o(digital) 60k pull-down 17 i2s_lrclk left/right strobe for i2s port (fs) i/o(digital) 60k pull-down 18 i2c_clk aux mode contro l port clock i(digital) 19 i2c_dat aux mode control port data i/o(digital) 20 vreffilt analog virtual ground o(analog) none 21 cap2 reference filter cap o(analog) none 22 vrefout-a reference voltage out drive (intended for mic bias) o(analog) none 23 i2s_din data input for i2s port (port f) i(digital) 60k pull-down 24 m ono _o ut mono output o(analog) none 25 avss1 analog ground i(analog) none 26 avdd1 analog vdd=5.0v or 3.3v i(analog) none 27 porta_l (hp0) port a output left i/o(analog) none 28 porta_r (hp0) port a output right i/o(analog) none 29 avss analog ground i(analog) none 30 portb_l (hp1) port b output left i/o(analog) none 31 portb_r (hp1) port b output right i/o(analog) none 32 avss analog ground i(analog) none 33 v- negative analog supply o(analog) none 34 cap- charge pump cap - o(analog) none 35 cap+ charge pump cap + o(analog) none 36 table 37. pin table
idt confidential 301 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo vreg linear regulator ou tput (2.5v) filter cap o(analog) none 37 avdd2 analog supply for vreg i(analog) none 38 pvdd analog supply for class-d amp i(analog) none 39 portd_+l btl amp left + o(analog) none 40 portd_-l btl amp left - o(analog) none 41 pvss analog ground i(analog) none 42 portd_-r btl amp right - o(analog) none 43 portd_+r btl amp right + o(analog) none 44 pvdd analog supply for class-d amp i(analog) none 45 dmic1/gpio/spdifout1/ aux_in digital microphone input, spdif output, or gpio0 i/o(digital) 60k pull-down 46 eapd eapd i/o (digital) 60k pull-up 47 spdifout0/aux_out spdif0 o(digital) 60k pull-down 48 pin name pin function i/o internal pull-up/pull-down 48 pin location table 37. pin table
idt confidential 302 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 8.0.2. 48qfn package outline and package dimensions package dimensions are kept curr ent with jedec publication no. 95 figure 27. 48qfn package diagram key qfn dimensions in mm min nom max a 0.80 0.90 1.0 a1 0.00 0.02 0.05 a3 0.20 ref d 7.00 bsc d1 5.50 bsc e 7.00 bsc e1 5.50 bsc l 0.35 0.40 0.45 e 0.50 bsc r 0.20-0.25 b 0.18 0.25 0.30 d2 5.50 5.65 5.80 e2 5.50 5.65 5.80 zd 0.75 bsc ze 0.75 bsc additional approved option
idt confidential 303 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 8.1. standard reflow profile data note: these devices can be hand soldered at 360 o c for 3 to 5 seconds. from: ipc / jedec j-std-020c ?moisture/reflow se nsitivity classification for nonhermetic solid state surface mount devices? (www.jedec.org/download). profile feature pb free assembly average ramp-up rate (ts max - tp) 3 o c / second max preheat: temperature min (ts min ) temperature max (ts max ) time (ts min - ts max ) 150 o c 200 o c 60 - 180 seconds time maintained above: temperature (t l ) time (t l ) 217 o c 60 - 150 seconds peak / classification temperature (tp) see ?package classification reflow temperatures? time within 5 o c of actual peak temper ature (tp) 20 - 40 seconds ramp-down rate 6 o c / second max time 25 o c to peak temperature 8 minutes max note: all temperatures refer to topside of the package, measured on the package body surface. table 38. standard reflow profile
idt confidential 304 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 9. disclaimer while the information presented he rein has been checke d for both accuracy an d reliability, manufac- turer assumes no responsibility for ei ther its use or for th e infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal co mmercial applications. any other applications, such as those requiring extended temper ature range, high reliability, or other extraord inary environmental requirements, are not recommended without additi onal processing by manufacturer. manufacturer reserves the right to change any circuitry or spec ifications without notice. manufacturer does not authorize or warrant any product for use in life support devices or critic al medical instruments.
idt confidential 305 v 1.1 1/12 ?2009 integrated device technology, inc. 92HD92 92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 10. document revision history revision date description of change 0.5 january 2010 initial release 0.8 march 2010 added widget details, front page feature bullet updates 0.85 june 2010 port e updated to add hphnen r/w bit in the pi n cntrl widget and as hpcapable in the widget capabilities. aux mode section updated to include additional information. 0.9 september 2010 added changes for ya silicon revision (za/zb prior settings referenced) afg eapd bit added for porte headphone control. afg comjack bits added to select debounce time.removed scs support. updated spkvol l/r step size to .75db and changed register address from 04/05h to 01/02h. added 3rd i2c regi ster for updating speaker l and r volume at the same time (to match hda implementation). additi onal i2c register bits added/reordered to r17, r19, r39, r40, r41, r42. i2c register r6 4 to r70 added.removed pull up from pins 19/20. updated conditions of performance characteristics, added hda signalling voltage to condition for power measurements. default changed on btl/ hd_mode from 0 to 1. updated record path behavior tabel for aux mode. added pin configuration default settings.corrected combo jack diagram. 0.91 october 2010 updated ldo level control values. corrected step size and thermal trip in btl section. clarified auxmode section wording related to d3cold entry. added description text for high pass and mono band pass filter features. 0.92 may 2011 corrected sense a/b description and table. 0.93 june 2011 corrected front page bullet for btl voltage and removed blank section 3. 1.0 october 2011 corrected left vs right channel for the eq coefficients to match silicon. updated electrical characteristics for typical values . removed preliminary. removed comments related to za and zb silicon since they were non-production. added wb silicon widget items: combojacktiming in the afg and scstabletimesel added to afg anabtl. added pvdd value for the digital maximum supply voltage and footnote to the gpio characteri stics for the input low and high voltage. added missing eapd wi dget details. 1.1 january 2012 updated i2c registers with reset information.
92HD92 single chip pc audio system, codec+speaker amplifier+capless hp+ldo 6024 silver creek valley road san jose, california 95138 disclaimer integrated device technology, inc. (idt) and its subs idiaries reserve the right to mo dify the products and/or specif ications de- scribed herein at any time and at idt?s sole discretion. all in formation in this document, including descriptions of product fe atures and perfor- mance, is subject to change without notice. performance specifications and the operati ng parameters of the described products a re determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the information co ntained herein is provided without repres entation or warranty of any kind, whether express or implied, including, but not limited to, t he suitability of idt?s products for any particular purpose, an implied warranty of merc hantability, or non-infringement of the intellectual property r ights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third pa rties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered trademarks of idt. other tra demarks and service marks used he rein, in- cluding protected names, logos and desi gns, are the property of idt or thei r respective third party owners.

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